ICTACT Journal on Microelectronics

Chahana Sharma ¹, Owais Ahmad Shah ¹

Affiliations
1 Department of Electrical and Electronics and Communication Engineering, Noida International University, IN

Abstract

In high-speed networks and applications of wireless communication systems, the wideband data transmission system needs to receive the signal with low noise and low power. The Low Noise Amplifier (LNA) improves the signal strength and amplify the signal at the receiver side to reduce the noise and also must work in the high speed switching activity. In the paper work, a low power and low noise with inductor-less active and passive model of trans-conductance (Gm) enhancement system in the 22nm CMOS technology. By using this type of CMOS technology, it reduces the power consumption due to the update channel width and circuit design of Gm enhancement. This paper also highlights in the reduction of overall area consumption with the alignment and other connectivity of amplifier. This amplifier was tested in both e-band and w-band operating frequencies to validate the noise level in high frequency applications. The result analysis and comparison chart shows the performance level of proposed LNA model than other state-of-art models.

Keywords

Low Noise Amplifier, Trans-Conductance Enhancement, CMOS, High Frequency Applications.

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Kajul Sahu ¹, Owais Ahmad Shah ¹

Affiliations
1 Department of Electronics and Communication Engineering, Noida International University, IN

Abstract

This paper presents comparative analysis of various flip-flops in CMOS technology. We simulated dual dynamic node hybrid flip flop (DDFF), Hybrid latch flip-flop (HLFF), Modified hybrid latch flip flop (MHLFF), and modified transmission gate flip flop (TGFF). The average power of various flip flops are calculated at 0%, 25%, 50% and 100% data activity, at temperature 25-100 ºC and different voltages 0.7, 0.9, 1 and 1.5. The average delay is also calculated at room temperature. All of these parameters are calculated in 32nm CMOS technology with the help of TSPICE. It was observed that MHLFF is the flop-flop that consumes less power compared to other flip flops. We are comparing performance and power dissipation and also compared transistor count of each flip flop.

Keywords

Average Power, Data Activity, Transistors, Average Delay, Edge Triggered Flip. Flop

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Rakesh ¹, Owais Ahmad Shah ¹

Affiliations
1 Department of Electronics and Communication Engineering, Noida International University, IN

Abstract

In this paper, various conditional flip flops topologies are simulated in 32nm CMOS technology using BSMv4 model and compared on the basis of Power consumption, delay (Clk to Q) and Power delay Product. In Various designs of conditional flip flops, our main objective is to optimize the best design on the basis of delay and power. Simulation results showed that by using Pulse Enhancement Scheme (PES) in flip flop, power dissipation is reduced to 59.43% when compared with conditional feed through flip flop technique and further reduction of 43.34% was observed in delay at room temperature. On increasing the temperature PES technique still have less power consumption of 35.95% when compare to conditional feed through flip flop technique. It was also observed that PES technique can be used at lower voltage levels. So that dissipation and delay both reduced. In terms of delay among all designs, Single ended conditional capturing energy recovery (SCCER) has minimum delay of 2.4865ns at room temperature and 2.4843ns at 1.5V power supply. Power delay product (PDP) at room temperature of SCCER is 0.7177aJ. These results of flip flop using conditional techniques at different temperature consideration and at different voltage give us an idea to choose which scheme is better in terms of delay, power consumption and PDP.

Keywords

Pulse Enhancement Scheme, SCCER, PDP, Power Dissipation.

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