ICTACT Journal on Microelectronics

Nitish ¹, Neeta Pandey ¹, Kirti Gupta ², Manu Kumar Saini ¹

Affiliations
1 Department of Electronics and Communication Engineering, Delhi Technological University, IN
2 Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, IN

Abstract

The quest to have longer battery life and reduced packaging cost has been motivating factor behind developing low power circuits for different applications. Research in adiabatic logic has recently gained momentum and diode free adiabatic logic (DFAL) is one among promising variant. This paper presents a diode free adiabatic logic (DFAL) based flexible multi-modulo prescaler. It provides frequency division of 32, 33, 47, 48, 64, 65, 79 and 80 based upon the value of control signals. The functionality and performance of the proposed prescaler is investigated through TSPICE simulations by using 0.18 micron TSMC technology parameters. The performance parameters average power dissipation, time delay and PDP of the DFAL based circuit are compared with its static CMOS counterpart and a maximum power saving of 84.6% is achieved.

Keywords

CMOS, DFAL, Dual-Modulo Prescaler, Multi-Modulo Prescaler.

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Neeta Pandey ¹, Venkatesh Kumar ¹, Aayush Goel ¹, Ankit Gupta ¹

Affiliations
1 Department of Electronics and Communication Engineering, Delhi Technological University, IN

Abstract

This paper presents Operational trans-resistance (OTRA) based electronically tunable high pass L-C based ladder filter. The proposed high pass filter is designed by following a systematic approach using leap frog simulation for ladder filters. The cut-off frequency of the proposed filter can be varied with the application of appropriate voltages to the gate of MOSFETs hence making the design electronically tunable. Therefore, it can be used for RF applications at 455kHz and 1MHz (intermediate frequencies for RF applications). Performance of the proposed circuit is verified through SPICE simulations employing a 0.5μm MOSIS AGILENT CMOS realization of OTRA.

Keywords

OTRA, High Pass Filter, Tunable.

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Sagar Jain ¹, Shubham Garg ¹, Neeta Pandey ¹, Kirti Gupta ²

Affiliations
1 Department of Electronics and Communication Engineering, Delhi Technological University, IN
2 Department of Electronics and Communication Engineering, Bharti Vidyapeeth’s College of Engineering, Delhi, IN

Abstract

The following manuscript proposes a modification to the existing PFAL based adiabatic structure called 2Phase PFAL for its operation on two phase sinusoidal power clocks and lower power dissipation. Sinusoidal shaped power clocks are easier to design and can be used to operate the adiabatic circuit in two phases. This proves to be advantageous as it reduces the on-chip routing complexity and density of the power-clock logic. Moreover usage of a two phase structure over a four phase structure for adiabatic operation reduces the phase consistency relationship requirement among the power clocks to realize the potential adiabatic gains. Conventional PFAL based approach requires the usage of buffers both at the input and output stages, increasing the buffer requirement. The proposed circuit is advantageous as it operates on two phases, reducing the buffer requirement leading to savings in area and power. Simulations using a standardized test bench have been performed for CMOS, PFAL and Proposed Logic based Inverter, Inverter Chain, NAND, NOR, XOR and XNOR structures. The results show that the proposed structure require less power as compared to its nearest competitors. Lower power dissipation with phase reduction, ease of power clock generation, reduced routing complexity and phase consistency relations among the power clocks make the proposed logic an suitable candidate for use in low power digital devices operating at low frequencies such as radio-frequency identifications (RFID`s), smart cards, and sensors.

Keywords

PFAL, 2Phase PFAL, CMOS, Sinusoidal.

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