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Arumugam, N.
- Drain Current Characteristics of Silicon Nanowire Field Effect Transistor
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 3 (2016), Pagination: 284-287Abstract
This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.Keywords
Nanowire Transistors, Drain Current Characteristics.
- Design of Adiabatic Logic Based Comparator for Low Power and High Speed Applications
Abstract Views :198 |
PDF Views:1
Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
2 Department of Electronics and Communication Engineering, Dr. Sivanthi Aditanar College of Engineering, IN
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
2 Department of Electronics and Communication Engineering, Dr. Sivanthi Aditanar College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 365-369Abstract
This paper presents a novel modified comparator based on the combination of 2N-2N2P adiabatic logic and two phase adiabatic static clocked logic (2N-2N2P and 2PASCL), combination of efficient charge recovery adiabatic logic and two phase adiabatic static clocked logic (ECRL and 2PASCL). This new structure computes a decision making signal faster than the existing methods. The introduced logic based comparator demonstrates that the usage of high speed decision making signal allows high speed comparator, saving 60-80% of power in comparison with existing renowned conventional comparators. Adiabatic logic based circuit carry out less power consumption by constraining current flowing through devices with less voltage drop and by reusing the energy stored at output node instead of discharging it to ground. The design is simulated using Cadence Virtuoso Environment.Keywords
Adiabatic Logic, ECRL, 2PASCL, 2N-2N2P, Comparator.References
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- Design and Analysis of InP and GaAs Double Gate MOSFET Transistors for Low Power Applications
Abstract Views :132 |
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, IN
2 Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, IN
1 Department of Electronics and Communication Engineering, National Engineering College, IN
2 Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, IN