Refine your search
Collections
Co-Authors
Journals
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
James, Marie K.
- Design and Read Stabilityanalysis of 8T Schmitt Trigger Based SRAM
Abstract Views :238 |
PDF Views:4
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 323-328Abstract
This paper presents an 8T Schmitt Trigger (ST) based SRAM design to improve the read stability and power dissipation of conventional 6T SRAM cell. The ST based SRAM cell incorporates built-in feedback mechanism in order to attain robust read operation. The read stability of the cell is 2.5× higher than that of 6T SRAM cell at 1.8V and it can retain data even at a lower Vmin of 0.3V. Also, power consumption is reduced by 22% compared to 6T SRAM design. The layout drawn using 120nm technology rule shows that the 8T ST SRAM occupies 1.2× higher area compared to 6T SRAM cell. Peripheral circuits for the 8T ST SRAM are introduced. Except the precharge circuit and basic SRAM cells, the remaining part of the circuitry is same for both single bit 6T and 8T ST SRAM array design. The single bit 8T ST SRAM array consumes less power and area in nano-scaled technologies. The proposed design was simulated in Mentor Graphics ELDO using TSMC 180nm technology.Keywords
Low Voltage SRAM, Schmitt Trigger, Read Stability, Read SNM.
References
- Yoshinobu Nakagome, Masahi Horiguchi, Takayuki Kawahara and K. Itoh, “Review and Future Prospects of Low-Voltage RAM Circuits”, IBM Journal of Research and Development, Vol. 47, No. 5-6, pp. 525-552, 2003.
- A.J. Bhavnagarwala, X. Tang and J.D. Meindl, “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, pp. 658-665, 2001.
- M.M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik and V. De, “Read and Write Circuit Assist Techniques for Improving Vccmin of Dense 6T SRAM Cell”, Proceedings of IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp. 185-189, 2008.
- K. Noda, K. Matsui, K. Takeda and N. Nakamura, “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology”, IEEE Transactions on Electron Devices, Vol. 12, No. 12, pp. 2851-2855, 2001.
- I. Carlson, S. Andersson, S. Natarajan and A. Alvandpour, “A High Density, Low Leakage, 5T SRAM for Embedded Caches”, Proceedings of 30th European Solid State Circuits Conference, pp. 215-218, 2004.
- B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, “A sub-200mV 6T SRAM in 0.13μm CMOS”, Proceedings of International Conference on Solid State Circuits, pp. 332-333, 2007.
- Sherif A. Tawfik and Volkan Kursun, “Low Power and Robust 7T Dual-Vt SRAM Circuit”, Proceedings of International Symposium on Circuits and Systems, pp. 1452-1455, 2008.
- N. Verma and A.P. Chandrakasan, “65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy”, Proceedings of International Conference on Solid State Circuits, pp. 328-329, 2007.
- Zhiyu Liu and Volkan Kursun, “High Read Stability and Low Leakage Cache Memory Cell,” Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2774-2777, 2007.
- Anis Feki et.al., “Sub-Threshold 10T SRAM Bit Cell with Read/Write XY Selection”, Solid-State Electronics, Vol. 106, No. 4, pp. 1-11, 2015.
- Ik Joon Chang, Jae-Joon Kim, Sang Phill Park and Kaushik Roy, “A 32 kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS”, IEEE Journal of Solid-State Circuits, pp. 388-622, 2008.
- Sangeeta Singh and Vikky Lakhmani, “Read and Write Stability of 6T SRAM”, International Journal of Advanced Research in Electronics and Communication Engineering, Vol. 3, No. 5, pp. 569-571, 2014.
- Nahid Rahman and B.P. Singh, “Design of Low Power SRAM Memory using 8T SRAM Cell”, International Journal of Recent Technology and Engineering, Vol. 2, No. 1 , pp. 123-127, 2013.
- S. Thirumala Devi and V.V.K. Raju, “Low Power Process Variation Tolerant Schmitt Trigger Based SRAM”, International Journal of Engineering Research & Technology, Vol. 2, No. 6, pp. 3194-3198, 2013.
- Jaydeep P. Kulkarni and Kaushik Roy, “Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 20, No. 2, pp. 319-332, 2012.
- Maheswary Sreenath and Binu K. Mathew, “Ultra Low Voltage, Low Power, Low Area, Process Variation Tolerant Schmitt Trigger based SRAM Design”, International Journal of Advanced Research in Computer Engineering and Technology, Vol. 2, No. 11, pp. 2817-2827, 2013
- A. Kishore Kumar, D. Somasundareswari, V. Duraisamy and T. Shunbaga Pradeepa, “Design of Low Power 8T Sram with Schmitt Trigger Logic”, Journal of Engineering Science and Technology, Vol. 9, No. 6, pp. 670- 677, 2014.
- R. Sandeep, Narayan T Deshpande and A.R. Aswatha, “Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies”, Proceedings of 2nd International Conference on Emerging Trends in Engineering and Technology, pp. 155-161, 2009.