ICTACT Journal on Microelectronics

M. C. Parameshwara ¹

Affiliations
1 Department of Electronics and Communication Engineering, Vemana Institute of Technology, IN

Abstract

Low power is a paramount concern in the design of ‘digital signal processor’ (DSP) for future multimedia applications. The quest to achieve low power has made the researchers to look into different techniques. In more recent years, the reversible logic is emerged as an alternate and promising low power technique for next generation technologies. It finds vast applications in nanotechnology, low power CMOS circuit design, approximate computing, optical computing, and quantum computing etc. The full adder being critical element of DSP plays an important role in the contribution of overall power of the system under consideration. This paper proposes a design of novel reversible full adder based on ‘carry-dependent sum full adder’ (CSFA) architecture using the standard reversible logic gates. The proposed reversible FA herein referred to as ‘Reversible CSFA’ (RCSFA). Two variants of RCSFA namely RCSFA-1 and RCSFA-2 have been proposed and discussed. To assess the merits of proposed RCSFAs, they are compared against the state-of-the-art reversible full adders (RFAs) in terms of quantum gate metrics (QGMs) such as number of gates, ‘quantum cost’ (QC), constant inputs, and garbage outputs etc. From the comparison results the proposed RCSFAs are found to be an alternative choice for designers in terms of QC, constant inputs and garbage outputs.

Keywords

Reversible Logic, Low Power, Full Adder, Quantum Gates, Quantum Cost.

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Chinna V. Gowdar ¹, M. C. Parameshwara ², Savita Sonoli ¹

Affiliations
1 Department of Electronics and Communication Engineering, Rao Bahadur Y Mahabaleshwarappa Engineering College, IN
2 Department of Electronics and Communication Engineering, Vemana Institute of Technology, IN

Abstract

Approximate or inexact computing is a well-established paradigm for designing error-tolerant applications such as image and digital signal processing. It is an interesting area of research, especially in the computer arithmetic designs. One key feature of this technique is that it reduces accuracy but still provides meaningful results with low power and reduced circuit complexity. This paper presents a comparative analysis of state-of-the-art approximate 1-bit full adders (AFA) for inexact computation. The performance of these AFAs are compared in terms of the design metrics (DMs) such as power, delay, and area. For a fair comparison, all AFAs under consideration have been described in Verilog register-transfer-level (RTL) codes and synthesized using Cadence’s RTL compiler. The synthesis is carried out using Cadence’s 180 nm standard cell library.

Keywords

Approximate Adder, Low Power, Approximate Computing, Full Adder, Inexact Adder.

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M. C. Parameshwara ¹

Affiliations
1 Department of Electronics and Communication Engineering, Vemana Institute of Technology, IN

Abstract

This research paper presents a novel 22-transistors (22T), 1-bit ‘full-adder’ (FA) for ‘Very-large-scale-integration’ (VLSI) applications. The proposed FA is derived from the hybrid logic, which is a combination of ‘gate-diffusion-input’ (GDI) technique, ‘transmission gate’ (TG) and ‘static CMOS’ (SCMOS) logic. To assess the performance of the proposed FA, it is compared with state-of-the-art FAs in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and ‘transistor count’ (TC). For a fair comparison, all FAs under consideration have been designed and simulated under common ‘process-voltage-temperature’ (PVT) conditions. The simulations have been conducted using Cadences’ Spectre simulator using 45 nm ‘predictive-technology-model’ (PTM). The simulations indicate that the proposed FA dissipates an ‘average power dissipation’ (APD) of 1.21 μW at an input signal frequency, fin=200 MHz and supply voltage, V_dd=1 V. It has a ‘worst case delay’ (WCD) of 135 ps and has a ‘power-delay-product’ (PDP) =0.163 fJ. Further to assess the scalability the proposed FA in terms of V_dd and input signal operand size, it is embedded in 64-bit(64b) ‘ripple carry adder’ (RCA) chain and simulations were conducted by scaling down the V_dd from 1.2 V to 0.4 V in steps of 0.2 V. The simulation results show that, only the proposed FA and other 2 reported as have the ability to operate in 64b RCA under different values of V_dd, without using any intermediate buffers. Further, it is observed that the proposed FA has a better power, delay, and TC as compared to the other 2 FAs.

Keywords

Full Adder, PDP, Low Power, Static CMOS, Gate-Diffusion-Input, Transmission-Gate-Logic.

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Chinna V. Gowdar ¹, M. C. Parameshwara ²

Affiliations
1 Department of Electronics and Communication Engineering, Rao Bahadur Y Mahabaleswarappa Engineering College, IN
2 Department of Electronics and Communication Engineering, Vemana Institute of Technology, IN

Abstract

This research paper presents the design of two 8×8 approximate multipliers based on novel approximate 3:2 and 2:2 compressors. The proposed multipliers are derived based on Wallace multiplier architecture and herein referred to as the proposed ‘approximate Wallace multiplier’ (AWM). The performance of these proposed AWMs has been assessed and analyzed in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. Further, a performance comparison of AWMs has been carried out against 6 other multipliers designed based on reported approximate 3:2 compressors. To extract these DMs, all the multipliers under consideration have been described using Verilog code and synthesized using Cadence’s ‘RTL Compiler’ (RC) tool using a 180 nm standard cell library. The synthesis results show that the proposed AWMs accomplish an excellent performance in terms of DMs. Further, the AWMs along with other designed Wallace multipliers, based on reported approximate compressors have been compared, under image processing application in terms of ‘peak signal-to-noise ratio’ (PSNR). The comparison results show that the proposed multipliers have a better PSNR (more than 50 dB).

Keywords

Approximate Computation, Wallace Multiplier, 3:2 Compressor, Low Power, PDP

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