ICTACT Journal on Microelectronics

K. Nandhini ¹, S. Arivazagan ¹

Affiliations
1 Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, IN

Abstract

In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.

Keywords

Verilog HDL, LSBMR, FPGA, Pipelining.

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B. Gomathi ¹, K. Nandhini ¹, C. K. Gobu ²

Affiliations
1 Department of Electronics and Communication Engineering, SNS College of Engineering, IN
2 Department of Electrical and Electronics Engineering, SNS College of Engineering, IN

Abstract

The main objective is to design a versatile silicon chip to curtail the power consumption and to shrink the global system area. The dynamic power consumption of digital FIR filters can be reduced by employing low power building blocks. Mathematically the neurons having the components of arithmetic and logical subsystems in the whole architecture. The power optimization is achieved by low power internal units of a system such as adder and multipliers. In this research the Finite Impulse Response (FIR) filter design is made by constructing Vedic multiplier with Dual Rail Domino Logic (DRDL) logic based adders. The proposed work consists of three major concepts, initially the DRDL based homogenous adder is constructed with several bit width, then secondly the multiplier is constructed by using proposed parallel adder. Finally, the filter is designed by combining this process. To make proposed FIR filter more effective, the FIR filter with Vedic multiplier is considered. These processes are described using structural Verilog-HDL and synthesized using Cadence RTL Compiler with respect to 90nm Cadence Generic Process Design Kit (GPDK) technological library.

Keywords

Dual Rail Domino Logic, Adder, Vertically Crosswise Multiplication, Finite Impulse Response, Power Delay Product.

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