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Jyothish Chandran, G.
- Design and Analysis of an Efficient Full Adder Using Systematic Cell Design Methodology
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 333-336Abstract
In this paper, a high performance and low power full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is initially executed for 1 bit and afterward reached out to 4 bit too. The circuit was implemented using Mentor Graphics tools at 180 nm technology. The performance parameters like average propagation delay, average power and Power Delay Product (PDP) are compared with existing hybrid adders like SRCPL adder and DPL adder. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The utilization of transmission gate all through the design guarantees high driving ability and full voltage swing at the output. The proposed adder is observed to work productively when compared with different adders in terms of average power, average propagation delay and PDP. The Schematic Driven Layout of the proposed adder is obtained using Mentor Graphics IC station and the physical verifications are done using Calibre tool.Keywords
Three Input XOR/XNOR, Systematic Cell Design Methodology, Transmission Gate, Full Adder, Low Power High Performance.
References
- C.H. Chang, J. Gu and M. Zhang, “A Review of 0.18-μm Full Adder Performances for Tree Structured Arithmetic Circuits”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 6, pp. 686-695, 2005.
- Sumeer Goel, Ashok Kumar and Magdy A. Bayoumi, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 12, pp. 1309-1321, 2006.
- Mariano Aguirre-Hernandez and Monico Linares-Aranda, “CMOS Full-Adders for Energy-Efficient Arithmetic Applications”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 19, No. 4, pp. 718-721, 2011.
- T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, “A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic”, Journal of Low Power Electronics, Vol. 5, No. 4, pp. 474-483, 2009.
- T. Nikoubin, M. Grailoo, and S. H. Mozafari, “Cell Design Methodology based on Transmission Gate for Low-Power High-Speed Balanced XOR- XNOR Circuits in Hybrid-CMOS Logic Style”, Journal of Low Power Electronics, Vol. 6, No. 4, pp. 503-512, 2010.
- Tooraj Nikoubin, Mahdieh Grailoo and Changzhi Li, “Energy and Area Efficient Three-Input XOR/XNORs with Systematic Cell Design Methodology”, IEEE Transactions on Very Large Scale Integration Systems, Vol.24, No. 1, pp. 398-402, 2016.
- Design Of High Performance Double Tail Comparator
Abstract Views :161 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 3 (2017), Pagination: 437-440Abstract
Comparator is an important building blocks used in analog-to-digital converters. Its function is to compare two analog inputs and delivers a logic value at the output. In this project an analysis on the delay of various dynamic comparators are presented. Based on the analysis a new dynamic comparator is designed for fast operations. Positive feedback mechanism is used to regenerate the analog input signal into full scale digital level. This design is a modification of conventional double-tail comparator. Addition of a few transistors to the conventional double-tail comparator results in remarkably reduced time delay. Kick-back noise of this comparator is also reduced. The large voltage variations in the internal nodes are coupled to the input nodes, which will disturb the input nodes-this is called kick-back noise. This is reduced by inserting switches before the input transistors of comparator. The performance of conventional comparator and proposed comparator circuits are evaluated based on Cadence 180nm CMOS process models.Keywords
Analog To Digital Converter (ADC), Double Tail Comparator, Kick Back Noise.References
- Samanesh Babayan-Mashhadi and Reza Lotfi, “Analysis and Design of a Low-Voltage-Power Double-Tail Comparator”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 2, pp. 343-352, 2014.
- D. Shinkel, E. Mensink, E. Klumperink, E. Van Tuiji and B. Nauta, “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 314-315, 2007.
- Pedro M. Figueiredo and Joao C. Vital, “Kick-back Noise Reduction Techniques for CMOS Latched Comparators”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 53, No. 7, pp. 541-545, 2006.
- B. Goll and H. Zimmermann, “A 0.12 μm CMOS Comparator requiring 0.5V at 600MHz and 1.5V at 6GHz”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 316-317, 2007.
- A. Mesgarani, M.N. Alam, F.Z. Nelson and S.U. Ay, “Supply Boosting Techniques for Designing very Low-Voltage Mixed-Signal Circuits in Standard CMOS”, Proceedings of 53rd IEEE International Midwest Symposium on Circuits and Systems, pp. 893-896, 2010.
- B. Goll and H. Zimmermann, “A 65nm CMOS Comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 328-329, 2009.
- B. Goll and H. Zimmermann, “A Comparator with Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65V”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 56, No. 11, pp. 810-814, 2009.
- Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparatos”, IEEE Transactions on Circuits and Systems-I: Regular papers, Vol. 56, No. 5, pp. 911-919, 2009
- P. Amaral, J. Goes, N. Paulino and A. Steiger-Garcao, “An Improved Low-Voltage Low-Power CMOS Comparator to be used in High-Speed Pipeline ADCs”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 141-144, 2002.
- Y. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D Converter”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 308-317, 2000.
- L.Y. Nathawad, R. Urata, B.A. Wooley and D.A.B. Miller, “A 40-GHz-Bandwidth, 4-bit, Time-Interleaved A/D Converter using Photoconductive Sampling”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp. 2021-2030, 2000.
- Ata Khorami and Mohammad Sharifkhani, “A High-Speed Method of Dynamic Comparators for SAR Analog to Digital Converters”, Proceedings of IEEE 59th International Midwest Symposium on Circuits and Systems, pp. 1-4, 2016.