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Kishore Parsediya, Deep
- Controlling Ambipolar Current And Enhancement Of On-state Current With High And Low Concentration Source Pockets
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Authors
Sudhan Kumar
1,
Dheeraj Singh Rajput
2,
Ritu Gupta
2,
Sankalp Shukla
2,
Deep Kishore Parsediya
3,
Vikash Sharma
4
Affiliations
1 Department of Electronics and Communication Engineering, National Institute of Technology, Goa, IN
2 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College, IN
3 Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science, IN
4 Department of Electronics and Communication Engineering, Rewa Engineering College, IN
1 Department of Electronics and Communication Engineering, National Institute of Technology, Goa, IN
2 Department of Electronics and Communication Engineering, Indira Gandhi Engineering College, IN
3 Department of Electronics and Communication Engineering, Madhav Institute of Technology and Science, IN
4 Department of Electronics and Communication Engineering, Rewa Engineering College, IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 1 (2022), Pagination: 1288-1294Abstract
This paper proposes and investigates a new architecture of PNPN TFET by using 2-D ATLAS Device Simulation Software TCAD Tool. The source pocket plays a crucial role in increasing the ON-state current through Tunnel FET. In order to enhance the source pocket characteristics, the source pocket is divided laterally into high and low concentration source pockets without modulating its width (LP). This modification results in a reduction of tunnelling width (λ), thereby increasing the significant amount of lateral electric field and suppressing the horizontal electric field, which in turn enhances the tunnelling probability as well as tunnelling rate. This proposed structure is a promising candidate for getting higher ON-state current (Ion), higher current ratio (Ion/Ioff), lower threshold voltage (VT) and reduced steepness sub-threshold slope (SS). These parameters are calculated with respect to conventional PNPN TFET and hetero-dielectric BOX (HDB) PNPN TFET, which enable the device to be operated efficiently with lower power consumption.Keywords
Band-to-Band Tunnelling (BTBT), Sub-Threshold Swing, Tunnelling Field-Effect Transistor (TFET), High-κ Dielectric, Hetero-Dielectric BOX (HDB)
References
- A.C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic”, Proceedings of the IEEE, Vol. 98, pp. 2095-2110, 2010.
- S.O. Koswatta, M.S. Lundstrom and D.E. Nikonov, “Performance Comparison between P-I-N Tunnelling Transistors and Conventional MOSFETs”, IEEE Transactions on Electron Devices, Vol. 56, pp. 456-465, 2007.
- J. Wana, C.L. Royer, A. Zaslavsky and S. Cristoloveanu, “Tunnelling FETs on SOI: Suppression of Ambipolar Leakage, Low-Frequency Noise Behavior, and Modeling”, Solid-State Electronics, Vol. 65, pp. 226-233, 2011.
- A.M. Ionescu and H. Riel, “Tunnel Field-Effect Transistors as Energy Efficient Electronic Switches”, Nature, Vol. 479, pp. 329-337, 2011.
- V. Nagavarapu, R. Jhaveri and J.C.S. Woo, “The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor”, IEEE Transactions on Electron Devices, Vol. 55, pp. 298-304, 2008.
- U.E. Avci, D.H. Morris and I.A. Young, “Tunnel Field-Effect Transistors: Prospects and Challenges”, IEEE Journal of the Electron Devices Society, Vol. 3, pp. 88-95, 2015.
- Hasanali G. Virani, Rama Bhadra Rao Adari and Anil Kottantharayil, “Dual-K Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs”, IEEE Transactions on Electron Devices, Vol, 53, pp. 57-66, 2010.
- Wei Cao, C.J. Yao, G.F. Jiao, Daming Huang, H.Y. Yu and Ming Fu Li, “Improvement in Reliability of Tunnelling Field-Effect Transistor With p-n-i-n Structure”, IEEE Transactions on Electron Devices, Vol. 56, pp. 1-23, 2011.
- Y. Qiu, R. Wang, Q. Huang and R. Huang, “A Comparative Study on the Impact of Interface Traps on Tunnelling FET and MOSFET”, IEEE Transactions on Electron Devices, Vol. 61, pp. 1284-1291, 2014.
- M. Schlosser, K.K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima and I. Eisele, “Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor with High-K Gate Dielectrics”, IEEE Transactions on Electron Devices, Vol. 56, pp. 100-108, 2009.
- A. Chattopadhyay and A. Mallik, “Impact of a Spacer Dielectric and a Gate Overlap/ Underlap on the Device Performance of a Tunnel Field-Effect Transistor”, IEEE Transactions on Electron Devices, Vol. 58, pp. 677-683, 2011.
- Jianzhi Wu and Yuan Taur, “Reduction of TFET OFF-Current and Subthreshold Swing by Lightly Doped Drain”, IEEE Transactions on Electronic Device, Vol. 63, pp. 1-14, 2016.
- Dawit Burusie Abdi and Mamidala Jagadesh Kumar, “In- Built N+ Pocket P-N-P-N Tunnel Field-Effect Transistor”, IEEE Electron Device Letters, Vol. 35, pp. 34-43, 2014.
- Shilpi Guin, Avik Chattopadhyay, Anupam Karmakar and Abhijit Mallik, “Impact of a Pocket Doping on the Device Performance of a Schottky Tunnelling Field-Effect Transistor”, IEEE Transactions on Electron Devices, Vol. 61, pp. 1-12, 2014.
- K. Boucart and A.M. Ionescu, “Double-Gate Tunnel FET with High-K Gate Dielectric”, IEEE Transactions on Electron Devices, Vol. 54, pp. 1725-1733, 2007.
- K.H. Kao, A.S. Verhulst, W.G. Vandenberghe and K. De Meyer, “Direct and Indirect Band-To-Band Tunnelling in Germanium-based TFETs”, IEEE Transactions on Electron Devices, Vol. 59, pp. 292-301. 2012.
- M. Madhini and Gaurav Saini, “Heterojunction Tunnel FET with Heterodielectric BOX”, Proceedings of International Conference on Communication and Signal Processing, pp. 1743-1746, 2016.
- Hao Wang, Sheng Chang and Gaofeng Wang, “A Novel Barrier Controlled Tunnel FET”, IEEE Electron Device Letters, Vol. 35, pp. 798-800, 2014.
- A. Hraziia, A. Gupta, A. Vladimirescu, A. Amara and C. Anghel, “30-nm Tunnel FET with Improved Performance and Reduced Ambipolar Current”, IEEE Transactions on Electron Devices, Vol. 58, pp. 1649-1654, 2018.
- Dae Woong Kwon, Jang Hyun Kim and Byung-Gook Park, “Effects of Drain Doping Concentration on Switching Characteristics of Tunnel Field-Effect Transistor Inverters”, Japanese Journal of Applied Physics, Vol. 55, pp. 1-14, 2016.
- Shubham Sahay and M. Jagadesh Kumar, “Controlling the Drain Side Tunnelling Width to Reduce Ambipolar Current in Tunnel FETs using Hetero-Dielectric BOX”, IEEE Transactions on Electron Devices, Vol. 62, pp. 3882-2886, 2015.
- ATLAS Device Simulation Software, “Silvaco”, Available at https://silvaco.com/tcad/, Accessed at 2015.
- Vishwa Prabhat and Aloke K. Dutta, “Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs”, IEEE Transactions on Electron Devices, Vol. 63, pp. 2190-2196, 2016.
- A.M. Walke, “Part I: Impact of Field-Induced Quantum Confinement on the Subthreshold Swing Behavior of Line TFETs”, IEEE Transactions on Electron Devices, Vol. 60, pp. 4057-4064, 2013.
- Ritesh Jhaveri, Venkatagirish Nagavarapu and Jason C.S. Woo, “Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor”, IEEE Transactions on Electron Devices, Vol. 58, pp. 80-86, 2010.
- W.G. Vandenberghe and M.V. Fischetti, “Impact of Field-Induced Quantum Confinement in Tunnelling Field-Effect Devices”, Applied Physics Letters, Vol. 98, pp. 143-150, 2011.
- X.D. Wang, Y. Xiong, M.H. Tang and J.H. He, “A Si Tunnel Field-Effect Transistor Model with a High Switching Current Ratio and Steep Sub-Threshold Swing”, Semiconductor Science and Technology, Vol. 29l pp. 1-5, 2014.
- Vandana Devi and Wangkheirakpam Brinda Bhowmick, “N+ Pocket Doped Vertical TFET Based Dielectric-Modulated Biosensor Considering Non-Ideal Hybridization Issue: A Simulation Study“, IEEE Transactions on Nanotechnology, Vol. 19, pp. 156-162, 2020.
- Tripty Kumari and Jawar Singh, “Investigation of Ring-TFET for Better Electrostatics Control and Suppressed Ambipolarity”, IEEE Transactions on Nanotechnology, Vol. 19, pp. 829-836, 2020.
- Weijun Cheng and Renrong Liang, “Fabrication and Characterization of a Novel Si Line Tunnelling TFET with High Drive Current“, IEEE Journal of the Electron Devices Society, Vol. 8, pp. 336-340, 2020.