ICTACT Journal on Microelectronics

V. Sujatha ¹, S. Ravindrakumar ², D. Sasikala ³, V. M. Senthil Kumar ⁴, N. V. Kousik ⁵, Jayasri Subramaniam ⁶

Affiliations
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB

Abstract

The transmission of clock signal is done across the integrated circuit in the presence of buffers and wires in synchronous biomedical systems on-chip architectures. This paper presents the investigation of the driver tree architecture to be used in microprocessor and DSP processors for biomedical image processing applications for clock distribution. In system on chip architecture this design plays an important role. Several clock distribution units like parallel, H-Bridge configurations were implemented in past. A new buffer is designed for the improvement of driving capability in clock distribution. This paper presents the CMOS based clock distribution circuit with better power and drive current. The parameters like power and current are investigated. Predictive technology models for CMOS 90nm technology are used.

Keywords

CMOS, Current Driver, Clock Driver, H-Bridge, Buffer, Power.

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