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Nelson, Bobby
- A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified GDI Cells for Low Power and Area Constraints
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Authors
Bobby Nelson
1,
Ravi Tiwari
1
Affiliations
1 Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, IN
1 Department of Electronics and Communication Engineering, Shri Shankaracharya Technical Campus, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 2 (2017), Pagination: 398-403Abstract
The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva-Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.Keywords
Area-Efficient, GDI, Karatsuba Algorithm, Multiplier, Urdhva-Tiryagbhyam Theorem.
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