ICTACT Journal on Microelectronics

C. S. Praveen ¹, Ajith Ravindran ¹, Shajimon K. John ¹, Susan Abe ¹

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN

Abstract

Increased power-dissipation in upcoming generation digital systems are limited by supply voltage reductions. For such systems, transistors with lower Subthreshold Slopes are needed. Tunnel Field Effect Transistors (TFET), which works on the principle of band-to-band tunnelling, are supposed to be the possible solution for this problem. TFETs ON-current (I_ON) is usually very low, with the use of semiconductors with indirect and large bandgap, and high effective mass as silicon, where tunnelling probability is depressed. One solution to this problem is the use of III-V semiconductors like InAs, GaSb, GaAsSb, In_xGa_1-xAs etc. and structure of gate is another important factor. Double gate instead of a single gate structure will provide improvement in ION. Work function of the gate material also has a great impact. In this paper, a study of the impact of In_0.53Ga_0.47As channel material, gate structure, work function and high-k dielectric for gate for TFET using Cogenda VTCAD is presented.

Keywords

Band to Band Tunnelling, Double Gate TFET, III-V Semiconductors, High-k Dielectric.

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Jitty Jose ¹, Ajith Ravindran ¹, Keerthi K. Nair ¹

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN

Abstract

Hetero-structured photodetector is a rapidly growing field of optoelectronic sensing for designing ultraviolet photodetectors of high efficiency and high responsivity. In recent years, one of the next generation semiconductor material ZnO, has attracted much attention in shorter wavelength optoelectronics devices and sensors. ZnO is considered as an ideal candidate in UV region because of its large exciton binding energy (60 meV), and wide bandgap energy (3.37eV). Naturally ZnO has n type conductivity and is very difficult to produce p type ZnO. Various p type materials such as Si, GaN, NiO, and Sr₂Cu₂O₂ have been used to realize p-n hetero junction photodetector. ZnO/Si based heterojunction devices have good electrical and optical properties, are easy to fabricate and has low deposition temperature. GaN is one of the propitious material in terms of considerably small lattice mismatch, less than 1.8% with ZnO and also exhibits similar lattice structure (wurtzite). ZnO/GaN structure exhibits high UV to visible rejection ratio and is very useful for high sensitive UV applications. The responsivity of n type ZnO with Si and GaN as substrate material is analyzed in this work. Also analyzed the various parameters that affects the responsivity of photo detector.

Keywords

Photodetector, Heterojunction, Responsivity, ZnO, GaN.

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K. S. Shilpa ¹, Ajith Ravindran ¹, P. M. Saranya ¹

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN

Abstract

Efforts to reduce power consumption of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for reducing dynamic and leakage power have been developed. These methods are implemented thoroughly in the circuit level. So we have to shift our concentration towards high level circuits. One of the example for high level circuit is a standard cell Application Specific Integrated Circuit (ASIC). Reducing the power and delay of standard cell ASIC can improve the performance of the system designed using these. A major contributor to the total power in modern microprocessors is the clock distribution network, which can dissipate as much as 70% of the total power for high performance applications. Self-gated resonant-clocked flip-flop optimized for power efficiency and signal integrity achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. The advantages of the Self gated resonant clocked flip-flop are implemented on standard cell ASICs. Cadence EDA tools and the 180nm process technology files have been used to substantiate the merits of the proposed design.

Keywords

Application Specific Integrated Circuit (ASIC), SGR Clocked Flip-Flop.

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