ICTACT Journal on Microelectronics

Thara Sebastian ¹, A. Aravindhan ¹

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN

Abstract

In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor 'AND' gate design and a pull up 'pMOS'. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. In this project, the effect of conditional pulse enhancement scheme on the power as well as performance of conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are analyzed. The performance analysis was carried out by adopting 180nm CMOS technology. The simulation results reveal that implicit flip flops with conditional pulse enhancement scheme outperforms the conventional flip flops in terms of power and timing characteristics.

Keywords

Pulse Triggered Flip Flop (P-FF), Pulse Control Scheme (PCS), Pulse Enhancement, Pass Transistor AND, Pulse Generation.

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Meenu Anna George ¹, A. Aravindhan ¹, G. Lakshminarayanan ²

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli, IN

Abstract

Network-on-chip (NoC) is a relatively new technology to signaling that enables not only more efficient interconnects but also more efficient design and verification processes for modern SoCs. The communication through the NoC is performed by enabling processing element (PE) to send and receive packets through the network fabric composed of switches/routers connected together through physical links or channels. For effective global on-chip communication, routers provide efficient routing with comparatively low complexity and high performance. Communication deadlock may appear at the router network and can cause performance degradation and system failure. Based on these studies, a five port priority based router is proposed. Port selection logic is used for selecting the ports for data transmission to selective ports. The proposed router shows better performance when tested in Mesh and Torus topology. Round Robin Algorithm is used in arbiter, which handles the process with priority and has low power consumption. The designed router is implemented in Artix 7, Spartan 6 and Virtex 7 using Xilinx ISE 14.7 design tool and power consumption of five port router is taken in Synopsis VHDL and power compiler tool.

Keywords

Network-On-Chip, Router, Communication Deadlock, Port Selection Logic, Round Robin Algorithm.

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S. Salini ¹, A. Aravindhan ¹, G. Lakshminarayanan ²

Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 Department of Electronics and Communicaiton Engineering, National Institute of Technology, Tiruchirappalli, IN

Abstract

Network on Chip (NoC) is a growing and prominent paradigm which improves the power and performance of the System on Chip (SoC). Application mapping is one of the major challenges in NoC which maps the various Intellectual Property (IP) cores to standard network topology. Among the various application mapping methods, Integer Linear programming (ILP) is one of the static mapping methods, which finds optimum communication cost. However, it consumes longer computation time. To overcome this limitation, cluster based mapping using KL algorithm has been introduced and it acts poorly at partitioning cut degree. Based on these studies, we propose Fidducia-Mattheyses (FM) algorithm for multi clustering to optimize power consumption and communication cost for different benchmarks of NoC. The effectiveness of the proposed method is verified through VOPD, MPEG 4 and PIP benchmarks. Experimental results show a 4.4% and 34% improvement on communication cost and power consumption respectively for FM algorithm with MPEG 4. However, for VOPD the communication cost and total power consumption is improved with 27% and 35% respectively. On the other hand, PIP benchmark offers identical results in total power consumed and communication cost minimization with existing methods.

Keywords

Application Mapping, Integer Linear Programming (ILP), Cluster Based Mapping, Fidducia-Mattheyses (FM) Algorithm.

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