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Case Study of Explicit and Implicit Pulsed Flip Flops with Conditional Pulse Enhancement Mechanism
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In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor 'AND' gate design and a pull up 'pMOS'. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. In this project, the effect of conditional pulse enhancement scheme on the power as well as performance of conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are analyzed. The performance analysis was carried out by adopting 180nm CMOS technology. The simulation results reveal that implicit flip flops with conditional pulse enhancement scheme outperforms the conventional flip flops in terms of power and timing characteristics.
Keywords
Pulse Triggered Flip Flop (P-FF), Pulse Control Scheme (PCS), Pulse Enhancement, Pass Transistor AND, Pulse Generation.
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- H. Kawaguchi and T. Sakurai, “A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, pp. 807-811, 1998.
- A.G.M. Strollo, D. De Caro, E. Napoli and N. Petra, “A Novel High Speed Sense-Amplifier-based Flip-Flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 11, pp. 1266-1274, 2005.
- H. Partovi, R. Burd, U. Salim, F.Weber, L. DiGregorio and D. Draper, “Flow-through Latch and Edge-Triggered Flip-Flop Hybrid Elements”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 138-139, 1996.
- S.D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T.J. Sullivan and T. Grutkowski, “The implementation of the Itanium 2 Microprocessor”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1448-1460, 2002.
- F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R.Wang, A. Mehta, R. Heald and G. Yee, “A New Family of Semi-Dynamic and Dynamic Flip Flops with Embedded Logic for High-Performance Processors”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 712-716, 1999.
- Neil H. E Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design”, 3rd Edition, Pearson Education, pp. 183-278, 2006
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev and V. De, “Comparative Delay and Energy of Single Edge-Triggered and Dual Edge Triggered Pulsed Flip-Flops for High-Performance Microprocessors”, Proceedings of International Symposium on Low Power Electronics and Design, pp. 147-152, 2001.
- P. Zhao, T. Darwish and M. Bayoumi, “High-Performance and Low Power Conditional Discharge Flip-Flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 477-484, 2004.
- Y.T. Hwang, J.-F. Lin and M.-H. Sheu, “Low Power Pulse Triggered Flip-Flop Design with Conditional Pulse Enhancement Scheme”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, pp. 361-366, 2012.
- P. Zhao, J. McNeely, W. Kaung, N. Wang and Z. Wang, “Design of Sequential Elements for Low Power Clocking System”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 914-918, 2011.
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