ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Trap Charges Induced Immunity in Dual Metal Gate (DMG) Junctionless Accumulation Mode (JAM) Nanowire FET (NWFET)


Affiliations
1 Department of Electronics and Communication Engineering, Maharshi Dayanand University, India
     

   Subscribe/Renew Journal


In this brief, we have done a comparative study of Single Metal Gate Junctionless Accumulation Mode Nanowire FET (SMG-JAM-NWFET) and Dual Metal Gate Junctionless Accumulation Mode Nanowire FET (DMG-JAM-NWFET) for their immunity against the trap induced charges. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the potential, current, transconductance and output conductance. Aberration in other parameters like drain characteristics, Subthreshold Slope, capacitances and cut-off frequency has also been studied deeply. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the aforesaid parameters. It is so because of the impact ionization effect, the resistance to trap charges in DMG-JAM-NWFET is much higher than SMG-JAM-NWFET.

Keywords

Immunity, Trap Charges, Junctionless Accumulation Mode, Drain Current, Transconductance Nanowire FET.
Subscription Login to verify subscription
User
Notifications
Font Size

  • G.E. Moore, “Cramming More Components onto Integrated Circuits”, Proceedings of the IEEE, Vol. 86, pp. 82-85, 1998.

  • F.D. Agostino and D. Quercia, “Introduction to VLSI Design (EECS 467), Short-Channel Effects in MOSFETs”, Available at http://www0.cs.ucl.ac.uk/staff/ucacdxq/projects/vlsi/report.pdf, Accessed at 2000.

  • R. Wang, J. Zhuge, R. Huang, Y. Tian, H. Xiao, L. Zhang, C. Li, X. Zhang and Y. Wang, “Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Proces Variation”, IEEE Transactions on Electron Devices, Vol. 54, No. 6, pp. 1288-1294, 2007.

  • L. Zhang, C. Ma, J. He, X. Lin and M. Chan, “Analytical Solution of Subthreshold Channel Potential of Gate Underlap Cylindrical Gate-all-Around MOSFET”, SolidState Electronics, Vol. 54, No. 8, pp. 806-808, 2010.

  • H. Abd El Hamid, B. Iniguez and J.R. Guitart, “Analytical Model of the Threshold Voltage and Subthreshold Swing of undoped Cylindrical Gate-all-around-based MOSFETs”, IEEE Transactions on Electron Devices, Vol. 54, No. 3, pp. 572-579, 2007.

  • D. Kumar, S. Singh, “Analytical Model of Triple Metal Stack Engineered Pocket Dielectric Gate All Around (TMSEPDGAA) MOSFET for Improved Analog Applications”, Silicon, Vol. 12, No. 2, pp. 1-15, 2021.

  • Kyung Rok Kim, Byung-Gook Park and In Man Kang. “RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs”, IEEE Transactions on Electron Devices, Vol. 58, No. 5, pp. 13881396, 2011.

  • Tae Kyun, Dong Hyun Kim, Young Gwang Yoon, Jung Min Moon, Byeong Woon Hwang, Dong-Il Moon and Gi Seong Lee, “First Demonstration of Junctionless AccumulationMode Bulk FinFETs with Robust Junction Isolation”, IEEE Electron Device Letters, Vol. 34, No. 12, pp. 1479-1481, 2013.

  • Manoj Kumar, Subhasis Haldar, S.S. Deswal, Mridula Gupta and R.S. Gupta. “Analytical Modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 29, No. 6, pp. 1036-1043, 2016.

  • Anubha Goel, Sonam Rewari, Seema Verma and R.S. Gupta, “High-K Spacer Dual-Metal Gate Stack Underlap Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET for High Frequency Applications”, Microsystem Technologies, Vol. 26, pp. 1697-1705, 2020.

  • Anubha Goel, Sonam Rewari, Seema Verma and R.S. Gupta, “Novel Dual-Metal Junctionless Nanotube FieldEffect Transistors for Improved Analog and Low-Noise Applications”, Journal of Electronic Materials, Vol. 50, pp. 108-119, 2021.

  • Anubha Goel, Sonam Rewari, Seema Verma and R.S. Gupta, “Physics-Based Analytic Modeling and Simulation of Gate-Induced Drain Leakage and Linearity Assessment in Dual-Metal Junctionless Accumulation Nano-Tube FET (DM-JAM-TFET)”, Applied Physics A, Vol. 126, pp. 1-14, 2020.

  • Anubha Goel, Sonam Rewari, Seema Verma, S.S. Deswal and R.S. Gupta, “Dielectric Modulated Junctionless Biotube FET (DM-JL-BT-FET ) Bio-Sensor”, IEEE Sensors, Vol. 21, No. 15, pp. 16731-16743, 2021.

  • Subhasis Haldar, Vandana Nath, S.S. Deswal and R.S. Gupta, “Numerical Modeling of Subthreshold Region of Junctionless Double Surrounding Gate MOSFET (JLDSG)”, Superlattices and Microstructures, Vol. 90, pp. 8-19, 2016.

  • Silvaco International, “Atlas User Manual: Device Simulator Software”, Available at https://www.eng.buffalo.edu/~wie/silvaco/atlas_user_manual.pdf, Accessed at 2020.

  • Anubha Goel, Sonam Rewari, Seema Verma and R.S. Gupta, “Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for Improved Gate Leakages, Analysis of Circuit and Noise Performance”, AEU-International Journal of Electronics and Communications, Vol. 111, No. 1, pp. 1-18, 2019.


Abstract Views: 211

PDF Views: 0




  • Trap Charges Induced Immunity in Dual Metal Gate (DMG) Junctionless Accumulation Mode (JAM) Nanowire FET (NWFET)

Abstract Views: 211  |  PDF Views: 0

Authors

Deepak Kumar
Department of Electronics and Communication Engineering, Maharshi Dayanand University, India
Shamsher Singh
Department of Electronics and Communication Engineering, Maharshi Dayanand University, India

Abstract


In this brief, we have done a comparative study of Single Metal Gate Junctionless Accumulation Mode Nanowire FET (SMG-JAM-NWFET) and Dual Metal Gate Junctionless Accumulation Mode Nanowire FET (DMG-JAM-NWFET) for their immunity against the trap induced charges. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the potential, current, transconductance and output conductance. Aberration in other parameters like drain characteristics, Subthreshold Slope, capacitances and cut-off frequency has also been studied deeply. It is so found that the DMG-JAM-NWFET poses much higher immunity against the trap charges as compared to the conventional SMG-JAM-NWFET in terms of much lower change in the aforesaid parameters. It is so because of the impact ionization effect, the resistance to trap charges in DMG-JAM-NWFET is much higher than SMG-JAM-NWFET.

Keywords


Immunity, Trap Charges, Junctionless Accumulation Mode, Drain Current, Transconductance Nanowire FET.

References