ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Schmitt-Trigger-Based Single-Ended Low-Power 8T Sram Cell


Affiliations
1 Department of Electronics and Instrumentation Engineering, Shri G.S. Institute of Technology and Science, India
     

   Subscribe/Renew Journal


This article presents a new design of a single-ended low-power 8 transistor (8T) Static Random-Access Memory (SRAM) bitcell based on Schmitt-Trigger. The proposed cell is designed using a single bitline architecture that eradicates the conflict of design requirements on the access transistors. The proposed cell uses a Schmitt-Trigger based inverter which helps to increase the hold, read and write ability of the bitcell. A selective power gating transistor is also used which increases the write ability and also lowers the power consumption during write operations. Various parameters such as signal to noise margin (SNM), delay, read/write power and leakage power consumption of the proposed bit cell are compared against the conventional 6T SRAM bitcell and other bitcells. The simulations are performed using Cadence Virtuoso Software with a 180nm technology. The proposed bitcell has 1.3x larger area than the conventional bitcell. The results show that the proposed bitcell compares well against all the other considered bitcells and also is a better performer in many parameters.

Keywords

Static Random-Access Memory (SRAM), Low-Power, Stability, Static Noise Margin (SNM), Schmitt-Trigger.
Subscription Login to verify subscription
User
Notifications
Font Size

  • S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan and Y. Xie, “Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies”, Proceedings of Asia and South Pacific Conference on Design Automation, pp. 1-8, 2005.

  • B. Wang, T.Q. Nguyen, A.T. Do, J. Zhou, M. Je and T.T. Kim, “Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, pp. 441-448, 2015.

  • J.M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuits- A Design Perspective”, 2nd Edition, Prentice Hall, 2004.

  • International Technology Roadmap for Semiconductors, Available at http://www.itrs.net/links/2013/chapters/2013 Executive Summary.pdf, Accessed at 2013.

  • S.R. Sridhara, M. DiRenzo, S. Lingam, S. Lee, R. Blazquez, J. Maxey, S. Ghanem, Y. Lee, R. Abdallah, P. Singh and M. Goe, “Microwatt Embedded Processor Platform for Medical System-on-Chip Applications”, Proceedings of International Symposium on VLSI Circuits, 2010.

  • S. Pal and A. Islam, “Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, pp. 549-558, 2016.

  • A.J. Bhavnagarwala, X. Tang and J.D. Meindl, “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability”, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 658-665, 2001.

  • T.H. Kim, J. Liu, J. Keane and C.H. Kim, “Circuit Techniques for Ultra-Low Power Subthreshold SRAMs”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1-14, 2008.

  • F. Moradi, D. Wisland, Y. Berg, S. Aunet and T. V. Cao, “Process Variations in Sub-Threshold SRAM Cells in 65nm CMOS”, Proceedings of IEEE International Conference on Microelectronics, pp. 121-129, 2010.

  • Sung Mo Kang and Yousuf Leblebici, “CMOS Digital Integrated Circuits Analysis and Design”, 3rd Edition, Tata McGraw Hill, 2003.

  • S. Ataei, J.E. Stine and M.R. Guthaus, “A 64 KB Differential Single-Port 12T SRAM Design with a Bit-Interleaving Scheme for Low-Voltage Operation in 32 nm SOI CMOS”, Proceedings of IEEE International Conference on Computer Design, pp. 1-6, 2016.

  • A. Venkatareddy, R. Sithara, Y.B.N. Kumar and M.H. Vasantha, “Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell”, Proceedings of International Conference on VLSI Design, pp. 337-343, 2016.

  • B. Madiwalar and B.S. Kariyappa, "Single Bit-Line 7T SRAM Cell for Low Power and High SNM”, Proceedings of International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing, pp. 8881-8887, 2013.

  • Z. Liu and V. Kursun, “Characterization of a Novel Nine-Transistor SRAM Cell”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 16, pp. 488-492, 2008.

  • L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, L. Sekaric, S. J. McNab, A.W. Topol, C.D. Adams, K.W. Guarini and W. Haensch, “Stable SRAM Cell Design for the 32 nm Node and Beyond”, Proceedings of International Conference on VLSI Technology, pp. 1-14, 2005.

  • S. Lin, Y.B. Kim and F. Lombardi, “Design and Analysis of a 32nm PVT tolerant CMOS SRAM Cell for Low Leakage and High Stability”, Integration, Vol. 43, pp. 176-187, 2010.

  • R.E. Aly and M.A. Bayoumi, “Low-Power Cache Design using 7T SRAM Cell”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, pp. 318-322, 2007.

  • I.J. Chang, J. Kim, S.P. Park and K. Roy, “A 32 kb 10T Sub-Threshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 44, pp. 650-658, 2009.

  • S. Ahmad, M. K. Gupta, N. Alam and M. Hasan, “Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, pp. 2634-2642, 2016.

  • C. Shalini and S. Rajendar, “CSI-SRAM: Design of CMOS Schmitt Trigger Inverter based SRAM Cell for Low Power Applications”, Proceedings of International Conference on Energy, Communication, Data Analytics and Soft Computing, pp. 231-241, 2017.

  • K. Cho, J. Park, T. W. Oh and S. Jung, “One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, pp. 1551-1561, 2020.

  • H. Rasekh, M. Sadeghi, A. Golmakani and M. Ali, “Design of Stable SRAM Cells based on Schmitt Trigger”, Proceedings of International Conference on Embedded Computing, pp. 1-13, 2014.

  • E. Seevinck, F.J. List and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells”, IEEE Journal of Solid-State Circuits, Vol. 22, pp. 748-754, 1987.

  • H. Qiu, T. Mizutani, T. Saraya and T. Hiramoto, “Comparison and Statistical Analysis of Four Write Stability Metrics in Bulk CMOS Static Random Access Memory Cells”, Japanese Journal of Applied Physics, Vol. 54, No. 2, pp. 4-9, 2015.

  • E. Grossar, M. Stucchi, K. Maex and W. Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies”, IEEE Journal of Solid-State Circuits, Vol. 41, pp. 2577-2588, 2006.

  • J.P. Kulkarni, K. Kim and K. Roy, “A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM”, IEEE Journal of Solid-State Circuits, Vol. 42, pp. 2303-2313, 2007.

  • G. Pasandi and S. M. Fakhraie, “A 256-kb 9T Near-Threshold SRAM With 1K Cells per Bitline and Enhanced Write and Read Operations”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, pp. 2438-2446, 2015.

  • S. Akashe, S. Bhushan and S. Sharma, “Modeling and Simulation of High-Level Leakage Power Reduction Techniques for 7T SRAM Cell Design”, AIP Conference Proceedings, Vol. 1476, pp. 35-41, 2012.

  • S.R. Mansore, R.S. Gamad and D.K. Mishra, “A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications”, Proceedings of IEEE International Symposium on Nanoelectronic and Information Systems, pp. 1-12, 2017.


Abstract Views: 227

PDF Views: 0




  • Schmitt-Trigger-Based Single-Ended Low-Power 8T Sram Cell

Abstract Views: 227  |  PDF Views: 0

Authors

Sarthak Jain
Department of Electronics and Instrumentation Engineering, Shri G.S. Institute of Technology and Science, India
R. S. Gamad
Department of Electronics and Instrumentation Engineering, Shri G.S. Institute of Technology and Science, India
R. C. Gurjar
Department of Electronics and Instrumentation Engineering, Shri G.S. Institute of Technology and Science, India

Abstract


This article presents a new design of a single-ended low-power 8 transistor (8T) Static Random-Access Memory (SRAM) bitcell based on Schmitt-Trigger. The proposed cell is designed using a single bitline architecture that eradicates the conflict of design requirements on the access transistors. The proposed cell uses a Schmitt-Trigger based inverter which helps to increase the hold, read and write ability of the bitcell. A selective power gating transistor is also used which increases the write ability and also lowers the power consumption during write operations. Various parameters such as signal to noise margin (SNM), delay, read/write power and leakage power consumption of the proposed bit cell are compared against the conventional 6T SRAM bitcell and other bitcells. The simulations are performed using Cadence Virtuoso Software with a 180nm technology. The proposed bitcell has 1.3x larger area than the conventional bitcell. The results show that the proposed bitcell compares well against all the other considered bitcells and also is a better performer in many parameters.

Keywords


Static Random-Access Memory (SRAM), Low-Power, Stability, Static Noise Margin (SNM), Schmitt-Trigger.

References