ICTACT Journal on Microelectronics

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The Efficient Implementation to Optimize Power and Delay Using Data Selector


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1 Department of Electronics and Communication Engineering, Sree Dattha Group of Institutions, India
     

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The objective of this paper is designing a 16:1 multiplexer using logic gates and CMOS logic. In this research, we have investigated the delay and power modulations of 16:1MUX. This demonstrates that the CMOS technique takes lead as it uses decreased number of transistors, have less capacitances and faster than others. In this research a comparative work is done and made the simulated results and it illustrates the superior nature of CMOS logic design and it dissipates very decreased power and delay. The simulations for the proposed model are done by using Synopsys tool HSPICE under 32 nm BSIM 4 model card for bulk CMOS technology of PTM model and examined the results with varying voltages. The minimum and maximum delay and power dissipation results are 68.82ps, 92.16ps and 103.96 μ W, 1471.4 μ W respectively. The overall transistor count we got in the Multiplexer is 282 and this is simulated and we got output waveforms of the MUX by using the advanced tool called HSPICE and they are represented in the results section.

Keywords

Multiplexer, 2 × 1 Multiplexer, 4 × 1 Multiplexer, 8 × 1 Multiplexer, 16 × 1 Multiplexer, Delay, Power Dissipation.
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  • The Efficient Implementation to Optimize Power and Delay Using Data Selector

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Authors

Jogi Prakash
Department of Electronics and Communication Engineering, Sree Dattha Group of Institutions, India
Biroju Ravi Kiran
Department of Electronics and Communication Engineering, Sree Dattha Group of Institutions, India
Parvatham Sathish
Department of Electronics and Communication Engineering, Sree Dattha Group of Institutions, India

Abstract


The objective of this paper is designing a 16:1 multiplexer using logic gates and CMOS logic. In this research, we have investigated the delay and power modulations of 16:1MUX. This demonstrates that the CMOS technique takes lead as it uses decreased number of transistors, have less capacitances and faster than others. In this research a comparative work is done and made the simulated results and it illustrates the superior nature of CMOS logic design and it dissipates very decreased power and delay. The simulations for the proposed model are done by using Synopsys tool HSPICE under 32 nm BSIM 4 model card for bulk CMOS technology of PTM model and examined the results with varying voltages. The minimum and maximum delay and power dissipation results are 68.82ps, 92.16ps and 103.96 μ W, 1471.4 μ W respectively. The overall transistor count we got in the Multiplexer is 282 and this is simulated and we got output waveforms of the MUX by using the advanced tool called HSPICE and they are represented in the results section.

Keywords


Multiplexer, 2 × 1 Multiplexer, 4 × 1 Multiplexer, 8 × 1 Multiplexer, 16 × 1 Multiplexer, Delay, Power Dissipation.

References