ICTACT Journal on Microelectronics

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VLSI Usage of a Productive MBIST Architecture Utilizing RLFSR


Affiliations
1 Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, India
2 Department of Electronics and Communication Engineering, Hindusthan College of Engineering and Technology, India
     

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This article introduces a power efficient application of FPGA created through a Memory Built in Self Test (MBIST). It has 2-bit Linear Feedback Shift Register (LFSR) array, which changes the direction of the previous process and creates high MBIST structures. This unwanted change affects all MBIST’s power consumption. The proposed MBIST with LFSR ring reduces the power consumption problem. The 2-bit 2N bit model generator is connected to the 2-bit (N-2) and 2-bit 4-bit (N-2) LFSR model generator, which are separately controlled using two separate clocks with two different frequencies, creating each location address high memory test. The proposed architecture has been implemented on Vertex4 FPGA technology in Xilinx software. The results enhance proposed design’s performance when compared it with the existing design.

Keywords

Xilinx, FPGA, Switching Activity, 2D-LFSR, Ring LFSR (RLFSR), Memory Built in Self Test (MBIST).
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  • VLSI Usage of a Productive MBIST Architecture Utilizing RLFSR

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Authors

K. Sivakami
Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, India
P. Vijayalakshmi
Department of Electronics and Communication Engineering, Hindusthan College of Engineering and Technology, India
J. Jaya
Department of Electronics and Communication Engineering, Hindusthan College of Engineering and Technology, India

Abstract


This article introduces a power efficient application of FPGA created through a Memory Built in Self Test (MBIST). It has 2-bit Linear Feedback Shift Register (LFSR) array, which changes the direction of the previous process and creates high MBIST structures. This unwanted change affects all MBIST’s power consumption. The proposed MBIST with LFSR ring reduces the power consumption problem. The 2-bit 2N bit model generator is connected to the 2-bit (N-2) and 2-bit 4-bit (N-2) LFSR model generator, which are separately controlled using two separate clocks with two different frequencies, creating each location address high memory test. The proposed architecture has been implemented on Vertex4 FPGA technology in Xilinx software. The results enhance proposed design’s performance when compared it with the existing design.

Keywords


Xilinx, FPGA, Switching Activity, 2D-LFSR, Ring LFSR (RLFSR), Memory Built in Self Test (MBIST).

References