ICTACT Journal on Microelectronics

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Designing of Variations Tolerant Sensing Amplifier Circuit for Deep Sub-Micron Memories


Affiliations
1 Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
2 Department of Electrical and Instrumentation Engineering, Sant Longowal Institute of Engineering and Technology, India
     

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In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30 % higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.

Keywords

Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness.
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  • Designing of Variations Tolerant Sensing Amplifier Circuit for Deep Sub-Micron Memories

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Authors

Vivek Harshey
Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
S. K. Bansal
Department of Electrical and Instrumentation Engineering, Sant Longowal Institute of Engineering and Technology, India

Abstract


In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30 % higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.

Keywords


Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness.

References