ICTACT Journal on Microelectronics

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Design of 1kB SRAM Array Using Enhanced Stability 10t SRAM Cell for FPGA Based Applications


Affiliations
1 Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
     

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SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

Keywords

SRAM Peripherals, Power, Delay.
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  • J. Samandari Rad, M. Guthaus and R. Hughey, “Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield”, IEEE Access, Vol. 2, pp. 577-601, 2014.

  • P. Singh and S. Vishvakarma. “Device/Circuit/Architectural Techniques for Ultra-Low Power FPGA Design”, Microelectronics and Solid State Electronics, Vol. 2, No. 1, pp. 1-15, 2013.

  • Y. Zhang, “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, pp. 199-213, 2013.

  • V. Sharma, N. Gupta, A.P. Shah, S.K. Vishvakarma and S.S. Chouhan, “A Reliable, Multi-Bit Error Tolerant 11T SRAM Memory Design for Wireless Sensor Nodes”, Analog Integrated Circuits and Signal Processing, Vol. 106, pp. 1-18, 2020.

  • B.H. Calhoun, J.F. Ryan and S. Khanna, “Flexible Circuits and Architectures for Ultralow Power”, Proceedings of IEEE, Vol. 98, No. 2, pp. 267-282, 2010.

  • V. Sharma and S. Kumar, “Design of Low-Power CMOS Cell Structures using Subthreshold Conduction Region”, International Journal of Scientific and Engineering Research, Vol. 4, No. 2, pp. 1-15, 2011.

  • F. Frustaci, M. Khayatzadeh, D. Blaauw, D. Sylvester and M. Alioto, “SRAM for Error-Tolerant Applications with Dynamic Energy-Quality Management in 28 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 50, No. 5, pp. 1310-1323, 2015.

  • R. Manoj Kumar and P.V. Sridevi, “A Proposed Low Standby Power Read Disturb-Free 9T SRAM Cell”, Proceedings of International Conference on Circuits and Systems in Digital Enterprise Technology, pp. 1-4, 2018.

  • R. Manoj Kumar and P.V. Sridevi, “Design of a Data-Independent Low Leakage Power 10T SRAM Cell”, ICTACT Journal on Microelectronics, Vol. 6, No. 3, pp. 976-980, 2020.

  • I.J. Chang, J.J. Kim, S.P. Park and K. Roy, “A 32 kb 10T Sub-Threshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS”, IEEE Journal on Solid-State Circuits, Vol. 44, pp. 650-658, 2009.

  • V. Sharma, P. Bisht, A. Dalal, M. Gopal, S.K. Vishvakarma and S.S. Chouhan, “Half-Select Free Bit-Line Sharing 12T SRAM with Double-Adjacent Bits Soft Error Correction and a Reconfigurable FPGA for Low-Power Applications”, International Journal of Electronics and Communications, Vol. 104, pp. 10-22, 2019.

  • S. Pal and A. Islam, “9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue”, IEEE Transactions on Device and Materials Reliability, Vol. 16, No. 2, pp. 172-182, 2016.

  • S. Gupta, K. Gupta, B. H. Calhoun and N. Pandey, “Low-Power Near-Threshold 10T SRAM Bit Cells with Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 3, pp. 1-11, 2018.

  • P. Sanvale, N. Gupta, V. Neema, A.P. Shah and S.K. Vishvakarma, “An Improved Read-Assist Energy Efficient Single Ended P-P-N based 10T SRAM cell for Wireless Sensor Network”, Microelectronics, Vol. 92, No. 1, pp. 1-15, 2019.

  • V. Sharma, M. Gopal, P. Singh and S. K. Vishvakarma, “A 220 mV Robust Read-Decoupled Partial Feedback Cutting Based Low-Leakage 9T SRAM for Internet of Things (IoT) Applications”, International Journal of Electronics and Communications, Vol. 87, pp. 144-157, 2018.

  • V. Sharma, S. Vishvakarma, S.S. Chouhan and K. Halonen, “A Write-Improved Low-Power 12T SRAM Cell for Wearable Wireless Sensor Nodes”, International Journal of Circuit Theory and Applications, Vol. 46, No. 12, pp. 2314-2333, 2018.

  • S. Gupta, K. Gupta and N. Pandey, “Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 10, pp. 3326-3337, 2018.

  • J. Kim and P. Mazumder, “A Robust 12T SRAM Cell with Improved Write Margin for Ultra-Low Power Applications in 40 nm CMOS”, Integration, Vol. 57, pp. 1-10, 2017.

  • L. Chang, “An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 956-963, 2008.

  • R. Manoj Kumar and P.V. Sridevi, “Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability”, Journal of Circuits, Systems and Computers, Vol. 13, No. 2, pp. 1-20, 2020.

  • P. Singh and S. Vishvakarma, “Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications”, Journal of Low Power Electronics and Applications, Vol. 7, No. 3, pp. 1-24, 2017.


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  • Design of 1kB SRAM Array Using Enhanced Stability 10t SRAM Cell for FPGA Based Applications

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Authors

R. Manoj Kumar
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
P. V. Sridevi
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India

Abstract


SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

Keywords


SRAM Peripherals, Power, Delay.

References