Design and Implementation of UART with FIFO Buffer using VHDL on FPGA

Universal Asynchronous Receiver Transmitter (UART) is a communication protocol commonly used for serial data communication. This paper presents the design and implementation method of a Universal Asynchronous Receiver Transmitter (UART) using VHSIC Hardware Description Language (VHDL). UART will be implemented to picoblaze processor which can be implemented in large system and have high flexibility in FPGA based design. UART controller has been designed using FIFO (First In First Out) buffer to avoid loss of data. Simulated and synthesized using Xilinx ISE 13.1. The design is successfully downloaded and verified on Spartan-3E FPGA board. The data that is sent will generate output LEDs on Spartan-3E. The total number of slice required is less than 10%. The number of slice Flip Flops are 1%, the total number of 4 input LUTs are 3% and the number of occupied slices are 3%. This design has a small resource.