Dynamic Fir Filter Schema Using Low Power Building Blocks

The main objective is to design a versatile silicon chip to curtail the power consumption and to shrink the global system area. The dynamic power consumption of digital FIR filters can be reduced by employing low power building blocks. Mathematically the neurons having the components of arithmetic and logical subsystems in the whole architecture. The power optimization is achieved by low power internal units of a system such as adder and multipliers. In this research the Finite Impulse Response (FIR) filter design is made by constructing Vedic multiplier with Dual Rail Domino Logic (DRDL) logic based adders. The proposed work consists of three major concepts, initially the DRDL based homogenous adder is constructed with several bit width, then secondly the multiplier is constructed by using proposed parallel adder. Finally, the filter is designed by combining this process. To make proposed FIR filter more effective, the FIR filter with Vedic multiplier is considered. These processes are described using structural Verilog-HDL and synthesized using Cadence RTL Compiler with respect to 90nm Cadence Generic Process Design Kit (GPDK) technological library.