ICTACT Journal on Microelectronics

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CNTFET Based Novel 14T Adder Cell For Low Power Computation


Affiliations
1 Department of Electrical and Electronics Engineering, Dayananda Sagar College of Engineering, India
2 Department of Telecommunication Engineering, Dayananda Sagar College of Engineering, India
     

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This paper focuses on the design of a 14 transistor one bit adder cell designed using CNTFET 32nm Technology to address the power and speed issues of high performance computational systems. The performance metrics of the proposed adder cell is compared by benchmarking with conventional full adder design, Transmission gate based full adder and Shannon’s expression based full adders using CNTFET technology. The proposed design has lesser delay and very low power consumption. The design embraces Stanford 32nm planar CNTFET library model with a power supply of 1 volt and single walled CNT. Extensive simulation has been carried out on the adder cells considered and the parameters such as power, delay and PDP are investigated. The effect of temperature variation on the power consumption of proposed 14T adder cell is also observed to examine the robustness. The simulation results demonstrate that the proposed adder delivers stable output drivability with substantial diminution in the leakage power.

Keywords

CNTFET, Adder Cell, Full Adder, Low Power, PDP.
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  • CNTFET Based Novel 14T Adder Cell For Low Power Computation

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Authors

S. Balaji Ramakrishna
Department of Electrical and Electronics Engineering, Dayananda Sagar College of Engineering, India
A. R. Aswatha
Department of Telecommunication Engineering, Dayananda Sagar College of Engineering, India

Abstract


This paper focuses on the design of a 14 transistor one bit adder cell designed using CNTFET 32nm Technology to address the power and speed issues of high performance computational systems. The performance metrics of the proposed adder cell is compared by benchmarking with conventional full adder design, Transmission gate based full adder and Shannon’s expression based full adders using CNTFET technology. The proposed design has lesser delay and very low power consumption. The design embraces Stanford 32nm planar CNTFET library model with a power supply of 1 volt and single walled CNT. Extensive simulation has been carried out on the adder cells considered and the parameters such as power, delay and PDP are investigated. The effect of temperature variation on the power consumption of proposed 14T adder cell is also observed to examine the robustness. The simulation results demonstrate that the proposed adder delivers stable output drivability with substantial diminution in the leakage power.

Keywords


CNTFET, Adder Cell, Full Adder, Low Power, PDP.

References