International Journal of Innovative Research and Development

N. Mohammad Subhani , R. Giri Prasad

Abstract

Global Positioning System (GPS) is a space-based global navigation satellite system. It provides time and location information to users anywhere on the Earth. The GPS receivers are placed in any embedded systems to continuously calculate current time, velocity and location information. Hence, real-time synchronous systems can be designed. The GPS receiver module is used for getting the location and time information in a predefined message frame through UART asynchronous serial communication. The main objective of this project is to design and development of FPGA based GPS data acquisition and processing system. FPGA is a better option to acquire the receiver data and it is to be processed further. FPGA will be interfaced to the GPS receiver module and the decoded received message like GPS latitude, longitude, altitude and velocity, with the proper Baud Rate. The internal signals are analyzed by using chip Scope pro tool. By using Geo-fencing concept we will generate Alarm and send information when the vehicle/objective exceeds the boundary, The FPGA data acquisition modules will be developed in hardware description language (VHDL) using Xilinx ISE Design suite and implemented and verified in Xilinx Development Board.

Keywords

GPS Receiver, Data Acquisition and Processtng System, FPGA (SPARTAN-3)

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D. Pradeep Kumar , R. Giri Prasad

Abstract

The paper presents the implementation of ultra low power 4-2 Compressor circuit operated by single-phase adiabatic Dynamic logic (SPADL) which, unlike any other existing Adiabatic logic family uses single sinusoidal supply-dock. This not only ensures high energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Static logic resembled characteristics of SPADL logic substantially decreases circuit complexity with improved driving ability and circuit robustness. In TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL saves 65% to 50% and 30% to 40% of total energy compared to Conventional CMOS and other existing single phase adiabatic logic based 4-2 Compressor for a frequency of 1MHz= to 100MHz.

Keywords

Single-phase, Adiabatic Logic, Energy Efficiency, High Speed, 4-2
Compressor

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