Reducing Leakage Current and Improving SRAM Cell Stability using Independent-Gate Finfet Technology Over Conventional CMOS Technology

In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. But the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So using CMOS SRAM beyond 45nm cell stability and controlling leakage current are becoming difficult in today's fast low power applications. FinFET may be an alternative of conventional CMOS transistor. In this paper independent double -gate FINFET structure based SRAM 6-Tcell has been proposed to controlling leakage current and improving SRAM cell stability. By adjusting threshold voltage (V_t) without affecting cell ratio we can reduce leakage current so that power during off state of transistor. In conventional CMOS due to heavy channel doping carrier mobilities are reduced which also increases process variations. In independent double gate FINFET technology, two separate gates are used. Threshold voltage of one gate can be altered by varying the voltage at the other gate. In this technology nearly intrinsic channel is used so carrier mobilities will be higher which results in higher speed of devices. Using the thin silicon fin, ratio of I_ON/I_OFF can also be increased. Due to vertical gate, there will no overlapping between source-gate and drain-gate so depletion and junction capacitances will be effectively eliminated. Wiring delay and bitline capacitance of SRAM will also be reduced.