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To Improve Register File Immunity against Soft Error


 

Gradually shrinking in feature size, increasing power density etc. Increase the vulnerability Of microprocessors against soft errors even in terrestrial Applications. The register file is one of the essential Architectural components where soft errors can occur in regular manner. This errors may rapidly spread from there throughout the whole system and the output results my get damage. Thus, register files are recognized as one of the major concerns when it comes to reliability. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection .we developed our project by using 64-bits register.

Keywords

ECC(ERROR CORRECTION CODE), FPGA(SPARTAN-3,XC3S400)
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  • To Improve Register File Immunity against Soft Error

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Abstract


Gradually shrinking in feature size, increasing power density etc. Increase the vulnerability Of microprocessors against soft errors even in terrestrial Applications. The register file is one of the essential Architectural components where soft errors can occur in regular manner. This errors may rapidly spread from there throughout the whole system and the output results my get damage. Thus, register files are recognized as one of the major concerns when it comes to reliability. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection .we developed our project by using 64-bits register.

Keywords


ECC(ERROR CORRECTION CODE), FPGA(SPARTAN-3,XC3S400)