FFT/IFFT Mixed Radix Processor for Wireless Applications

In this project a 128-point FFT/IFFT processor for ultra wideband (UWB) systems, FFT algorithm is used to reduce the computational complexity of DFT and to eliminate the redundant complex multiplication. The proposed pipelined FFT architecture called mixed radix multipath delay feedback (MRMDF) can provide a higher throughput rate achieved by using butterfly units. In addition the number of complex multiplications reduced effectively by using a higher radix algorithm. The 128-point mixed radix FFT/IFFT algorithm is implemented to power consumption and hardware cost can also be saved. Here memory based FFT architecture will decompose a larger FFT computation into several cascaded smaller FFTs and utilize a single FFT core to reduce the hardware cost.