Approximate Adder Design Using CPL Logic for Image Compression

Low power is an imperative requirement for portable multimedia devices for employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore it is not necessary to produce exactly the correct numerical outputs. Taking this fact into account, complexity reduction was done in the adder design, as adder design has become the most focused area in the VLSI design process to reduce the power consumption and to enhance the speed and overall performance of the system. In the previous work, the number of transistors was reduced in the conventional mirror adder based on certain approximations also the area comparison was done for the conventional mirror adder and its four approximations. In this paper a much more advanced Complementary Pass Transistors Logic (CPL) adders are used in the design for considering the approximations and the obtained area and power savings is compared with the previous work. The simulated results show area savings of 31.3% and power savings of 36%.