Power Consumption in Networks-on-Chip by Encoding Scheme

Power has become an important design criterion in modern system designs, especially in portable battery-driven applications. A significant portion of total power dissipation is due to the transitions on the off-chip address buses. This is because of the large switching capacitances associated with these bus lines. There are many encoding schemes in the literature that achieve a huge reduction in transition activity on the instruction address bus. However, on data and multiplexed address buses, none of the existing schemes consistently achieve significant reduction in transition activity. Also, many of the existing techniques add redundancy in space and/or time. In this paper, novel encoding schemes are proposed that significantly reduce transitions on these buses without adding redundancy in space or time. Also, for applications with tight delay constraints, configurations with minimal delay overhead while still achieving significant reduction in transition activity are proposed. Results show that, for various benchmark programs, these techniques achieve reduction of up to 54% in transition activity on a data address bus. On a multiplexed address bus, there is a reduction of up to 61% using our techniques. The proposed schemes are then compared with the existing schemes. It is seen that on an average, the reductions achieved by our techniques are twice those obtained using the current scheme on a data address bus and 55% more than those for multiplexed address bus.