Low Power Pulse Triggered Flip-Flop for Memory Applications

The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. Here a kind of conventional pulse-triggered flip-flop called Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop is designed. The comparison of low power pulse triggered flip-flops between DET, SVL logics is carried out and the best power -performance is obtained which is implemented as a memory application. The simulation results are obtained with Tanner simulation tool.