Improved Granularity of HW/SW Co-Simulation by using Pipelined Instruction Set Simulator

Processor simulator models are the integral part of nearly all modern SOC/ASIC virtual platforms, as they let the software development team to progress without the dependency on the silicon tape-out time. Important considerations while developing an Instruction Set Simulator are speed and accuracy, which generally comes at the cost of decreased granularity of the different stages of instruction life cycle. Mainstream processor ISS virtual models do not implement the pipelines, as it’s a bottleneck to the performance and increases code complexity when implemented in the languages as C, C+. This eradicates ISS model’s scope for system level program development like compiler design and architecture exploration of new processors, limiting its use only for pre-silicon software testing. In this paper we present a novel technique to implement pipelines using multi-threaded SystemC high level hardware modeling language, that provides better granular accuracy and enhanced instruction execution performance efficiency to the processor ISS over a similarly modeled no pipeline version of the ISS. Classic RISC 3 stage pipeline is taken as a reference for this design and implementation.