VLSI Implementation of Edge-Oriented Image Scaling Architecture

Image scaling is a resizing of digital image and it is a very important technique which has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling architecture. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality.

Resizing the image has become a significant trend to design a low-cost, high quality, and high performance image scalar by VLSI technique for multimedia electric products.

The image scaling is done by means of applying image interpolation methods. Image interpolation is that a method to increase or decrease the number of pixels in a digital image. Image interpolation is of two types namely adaptive interpolation and non adaptive interpolation. Various non adaptive algorithms are proposed for the image scaling, the nearest neighbour algorithm is the simplest method with low complexity and easy implementation. The seven-stage VLSI architecture of our image scaling processor yields a processing rate of about 157.072MHz using Xilinx Artix -7 FPGA device.