Online Built-In-Self Test Architecture Using SRAM Cells

In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM like structure to store the relative location of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and concurrent test latency (CTL) trade off. In this paper two methods will be discussed, window monitoring concurrent bist and input vector monitoring concurrent bist using sram,