AIRCC's International Journal of Computer Science and Information Technology

Nitin Chaturvedi ¹, Jithin Thomas ¹, S. Gurunarayanan ¹

Affiliations
1 Birla Institute of Technology and Science, EEE Group, Pilani, IN

Abstract

This paper is aimed at exploring the various techniques currently used for partitioning last level (L2/L3) caches in multicore architectures, identifying their strengths and weaknesses and thereby proposing a novel partitioning scheme known as Adaptive Block Pinning which would result in a better utilization of the cache resources in CMPs. The widening speed gap between processors and memory along with the issue of limited on-chip memory bandwidth make the last-level cache utilization a crucial factor in designing future multicore processors. Contention for such a shared resource has been shown to severely degrade performance when running multiple applications. As architectures incorporate more cores, multiple application workloads become increasingly attractive, further exacerbating contention at the last-level cache. Several Non-Uniform Cache Architecture (NUCA) schemes have been proposed which try to optimally use the capacity of last-level shared caches and lower access times on an average. This is done by continually monitoring the cache usage by each core and dynamically partitioning it so as to increment the overall hit ratio.

Keywords

Chip Multiprocessor, Non-Uniform Cache Architecture, L2 Cache.

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