AIRCC's International Journal of Computer Science and Information Technology

C. Ashok Kumar ¹, B. K. Madhavi ², K. Lal Kishore ³

Affiliations
1 ECE dept, TRR Engg. College, Hyderabad, AP, IN
2 ECE Dept., SNIST, Ghatkesar, Hyderabad, AP, IN
3 JNTU College of Engg., Kukatpally, Hyderabad, IN

Abstract

These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive feed back method is developed for the elimination of glitches in the CMOS circuitry, which result in power consumption and reducing performance of VLSI design. The optimized sequence is then processed through a 8-bit register bank modeled in CMOS level for data transfer to observe the glitch effect. Tanner EDA tool is used for the designing of the CMOS circuitry with resistive feedback mechanism for power optimization.

Keywords

Low Power VLSI, Glitch Free Modeling, Resistive Feedback Logic, Stray Capacitance.

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