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Authors
Affiliations
1 Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing 100190, CN
Source
AIRCC's International Journal of Computer Science and Information Technology, Vol 5, No 4 (2013), Pagination: 53-65
Abstract
A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents a test/repair flow based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, this paper for the first time proposes a robust post repair stage based on BIRA and memory grouping in test flow. Simulation results by mathematical method show that the proposed test flow has achieved a significant increase in yield of memories.
Keywords
Test Flow, Test, BISR, Multi-Memory.
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