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Authors
Affiliations
1 Digital System Group, Central Electronics Engineering Research Institute (CEERI)\
Council of Scientific and Industrial Research (CSIR), Pilani-333031 (Raj.), IN
Source
AIRCC's International Journal of Computer Science and Information Technology, Vol 1, No 2 (2009), Pagination: 80-87
Abstract
Partial reconfiguration allows time-sharing of physical resources for the execution of multiple functional modules by swapping in or out at run-time without incurring any system downtime. This results in dramatically increase in speed and functionality of FPGA based system. This paper presents the designing an interface controller through UART for execution&implementation of reconfigurable modules (RM) on Xilinx Virtex-4(XC4VFX12), (XC4VFX20) and (XC4VFX60) devices. To verify partial reconfiguration execution at run-time an interface has been designed to make user interaction with the system at run-time. Interface design includes the controllers for controlling the flow of data to and from the reconfigurable modules to the external world (host environment) through busmacros. The controller is designed as static module. All the static as well as dynamic modules are designed and simulated to verify the functionality with supporting simulation tool using ModelSim-6.0d and synthesized with Xilinx 9.1.02i_PR10 (ISE).
Keywords
Reconfigurable Computing Systems, Partial Reconfiguration, FPGA, Reconfigurable Modules, Busmacros.
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