Programmable Device Circuits and Systems

Fazal Noorbasha ¹, Shaik Moulali ¹, S. Dayasagar Chowdary ¹

Affiliations
1 Department of Electronics & Communication, KL University, Guntur (District), AP, IN

Abstract

In today‘s Integrated Circuits (ICs), Built-In-Self Test (BIST) is becoming increasingly important as designs become more and more complicated. BIST is beneficial in many ways:First, it can reduce dependency on external Automatic Test Equipment (ATE). In addition, BIST can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is crucial to the quality component of testing. BIST can overcome pin limitations due to packaging, make efficient use of available extra chip area, and provide more detailed information about the faults present. On a very basic level, BIST needs a stimulus (the Test Pattern Generator-TPG), a circuit to be tested (CUT) and a way to analyze the results (ORA). Additionally, there may be compression schemes for the TPG and the ORA. A 64 bit RISC processor with limited functionality will design with an architecture that supports BIST. The ALU is analyzed and an exhaustive set of test patterns will develop. Here clock gating technique is used for reducing the power consumption of the design. Some of these applications include vending machines, bottling plants, control of robotic movements, and automatic teller machine (ATM). Cadence tool is used for synthesis and Xilinx ISE is used for simulation.

Keywords

RISC, BIST, BISR, Memory, Clock Gating.

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Fazal Noorbasha ¹, S. Dayasagar Chowdary ¹, K. Hari Kishore ¹, Shaik Moulali ¹

Affiliations
1 Department of Electronics & Communication, KL University, Guntur District, IN

Abstract

LFSR's are the functional building blocks of circuits like the pseudo-random noise (PN) code generator that are commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an SR4 (Shift Register) primitive for area-efficient designs LFSR using the encryption and decryption algorithms using XOR gate in 180nm for less area and low power methodologies for ASIC designs using Cadence design tools. The unusual sequence of values generated by an LFSR can be gainfully employed in the encryption and decryption of data. That makes the cryptography quite easy and useful for longer bit lengths. A stream of data bits can be encrypted and decrypted by XOR-ing them with output from an identical LFSR's which finds the certain applications like Radio and visual broad casting schemes, Internet and Wireless communications. This work mainly concentrates on the 4 bit random number that uses for encryption that is mainly works faster clock rates of  100MHz, which finds the application in wireless networks.

Keywords

LFSR, Low Power, CDMA, Pseudo Random Noise Generator, XOR, Encryption and Decryption.

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