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Authors
Affiliations
1 Shree Venkateshwara Hi-Tech Engineering College, Tamilnadu, IN
2 Saveetha Engineering College, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 7, No 5 (2015), Pagination: 151-156
Abstract
The occurrence of errors is inevitable in modern VLSI Technology and to overcome all possible errors is an expensive task. It not only uses a lot of power but insults the speed performance. To create an output with the same width as the input, fixed width multipliers cut short the half least significant bits (LSBs) in DSP applications. This paper proposes an accuracy adjustment fixed width booth multiplier that compensates the truncation error using a multilevel conditional probability (MLCP) estimator and derives a closed form for various bit widths L and column information. Error Tolerant Adder (ETA) circuit a little bit can reduce the strict restriction on quality of being very close to the truth to accomplish extreme improvements in both the power use and flow performance, when its compared to conventional counterparts. The proposed MLCP estimator reduces test run time and easily changes to make better quality of being very close to the truth based on mathematical derivations. The proposed MLCP uses whole non-zero code, to guess the truncation error and accomplish higher levels. What's more, the simple and small MLCP made up for circuit is proposed. The proposed MLCP booth multipliers accomplish low cost high performance.
Keywords
ETA Adder, Multilevel Conditional Probability (MLCP), High Speed, Error Tolerant.
