Programmable Device Circuits and Systems

R. Anitha ¹, S. Bindhu ¹, Dhanya Menon ¹, P. Jyothi ¹, P. R. Vaya ¹

Affiliations
1 Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham, Bangalore Campus, IN

Abstract

Switched capacitor readout is the most widely used architecture for capacitive sensing. Capacitive sensing is based on charge-voltage relationship, the same foundation on which the SC circuits operate. SC circuit provides a virtual ground and robust dc biasing at the sensing node so that the sensed signal is insensitive to parasitic capacitance and undesirable charging. In switched capacitor circuits, the sense and reference capacitors are charged with opposite polarities and a packet of charge proportional to the capacitance difference is integrated on the input feedback capacitor. In this paper, the switched capacitor technique is incorporated into a simple inverting amplifier to study its significance in submicron IC technology. Analysis on the design constraints required for SC circuits is studied in the paper. Switched capacitor readout front end circuit uses correlated double sampling technique for finite gain, noise reduction and offset cancellation. Simulations are done using 180nm level 49 library with the supply tied at 5V. Circuit achieves a noise reduction of more than 50% and a significant reduction in area is observed.

Keywords

Amplifier, Correlated Double Sampling, Noise, Switched Capacitor.

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P. Jyothi ¹, R. Anitha ¹, S. Bindhu ¹, Dhanya Menon ¹, P. R. Vaya ¹

Affiliations
1 ECE Department, Amrita School of Engineering, Bangalore-560035, IN

Abstract

Although sigma-delta concepts existed since the middle of the century, only recent advances in VLSI technologies have made possible the appropriate handling of the bit stream generated by the 1-bit ADC. The spread spectrum nature of this noise shaping modulator suppresses the error in the baseband, thus improving dynamic range in the band of interest, independent of signal frequency. Paper presents a CMOS circuit design of second order sigma delta modulator with an option of selecting the order. Comparative study of first and second order sigma delta modulators is performed and best value of OSR is selected. The circuit is simulated in HSPICE 180nm level49 library. Analysis of the noise and power results of the first and second order ΣΔ modulator leads to the design of an order switchable sigma delta modulator, which is based on the resolution of ADC.

Keywords

Noise Shaping, Oversampling, Sigma Delta Modulator, Sinc Filter, SNR.

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M. Ponni ¹, Karthikeyan Ramamurthi ², P. R. Vaya ¹

Affiliations
1 ECE Department, Amrita School of Engineering, Bangalore-560035, IN
2 Intel Corporation, ORR, Bangalore, IN

Abstract

Binary addition is the most frequently used and speed limiting operation in the design of data path subsystems. There are several ways to formulate addition operation. Different ways provide different implementations. Among them, parallel prefix adder architectures are very much attractive because of their ease in formulation and implementation efficiency. In this paper, we are presenting the performance evaluation and comparison of 16-bit parallel prefix adder architectures namely Ladner-Fischer, Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. The comparison is done on the basis of three performance parameters i.e. area, power and delay. Out of these adders mentioned above, Han-Carlson architecture is found to be the best compromise.

Keywords

Parallel Prefix Adder, Synopsys.

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