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Annalakshmi, M.
- FPGA Implementation of Low Power Image Scaling Processor Using Bilinear Interpolation
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1 Department of VLSI Design, Sethu Institute of Technology, Kariapatti-626106, Tamilnadu, IN
2 Department of ECE, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN
3 VLSI Design, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN
1 Department of VLSI Design, Sethu Institute of Technology, Kariapatti-626106, Tamilnadu, IN
2 Department of ECE, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN
3 VLSI Design, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN