Programmable Device Circuits and Systems

M. Vaijayanthi ¹, K. Vivek ²

Affiliations
1 Electronics Department in Manakula Vinayagar Institute of Technology, Puducherry, IN
2 Manakula Vinayagar Institute of Technology, IN

Abstract

The ultra-low power and area efficient analog-to-digital converters (ADCs) makes use of low voltage CMOS dynamic comparators to maximize the power efficiency and speed. The conventional dynamic comparators have characteristics like high input impedance, no static power dissipation and good robustness against noise and mismatch. The drawback is that large numbers of transistors are used to reduce the offset, so the speed of the comparator is minimized. Double tail comparators overcome the drawbacks in conventional comparator by reducing the stacking of transistors with low supply voltage and delay. But there is a problem of low trans-conductance for this comparator. In modified double tail comparator, few transistors are added and the positive feedback in the regeneration stage is strengthened and the power consumption and delay time is reduced. In this paper delay analysis of dynamic double tail comparators are presented with respect to speed and supply voltage. Then based on the delay analysis results, the modified double tail dynamic comparator is modified in terms of architecture and transistor technology which results as body driven Double Tail Dynamic Comparator for fast operation even in ultra low supply voltages. Simulation results can be done by using 180nm CMOS technology reveals that the delay time is considerably reduced.

Keywords

Dynamic Comparators, Double Tail Comparators, Body Driven Double Tail Comparator, Regeneration, Delay Analysis.

Full Text

     

J. Ajayan ¹, S. Shriram ², D. Nirmal ³, K. Vivek ⁴

Affiliations
1 Electronics and Communication Engineering, Karunya University, IN
2 Electronics and Communication Engineering, MIT, Pondicherry, IN
3 Electronics and Communication Engineering Department, Karunya University, IN
4 Electronics and Communication Engineering, B. S. Abdur Rahman University, IN

Abstract

In this paper, a 128 bit high speed Manchester carry chain (MCC) adder is implemented using 22nm strained silicon technology with a supply voltage of 0.8V. The non-idealities such as variability and leakage current, may significantly degrade the performance of digital circuits as the technology approaches to nanometer regime. In this paper, the effect of temperature on the performance of the Manchester carry chain adder circuit is analyzed in detail and its performance is compared with the same circuit implemented using 90nm CMOS technology. The even and odd carries of the MCC adder are computed separately using two different carry chains. This will improves the operating speed of the adder. 8-Bit MCC adder modules are used for constructing 128 bit MCC adder.

Keywords

Carry Look-Ahead Adders, Domino Logic, High Performance, Leakage Currents, Manchester Carry Chain.

Full Text