Programmable Device Circuits and Systems

N. Kannaiya Raja ¹, K. Arulanandam ², B. Raja Rajeswari ³

Affiliations
1 Department of CSE, Arulmigu Meenakshi Amman College of Engg, Thiruvannamalai Dt., Near Kanchipuram, IN
2 Department of CSE, Ganadipathy Tulsi's Jain Engineering College, Vellore, IN
3 Arulmigu Meenakshi Amman College of Engg, Thiruvannamalai Dt., Near Kanchipuram, IN

Abstract

The network equipment has capable of inspecting packets in order to discover the worms and virus over the network. Many network users are hacked by attackers through malicious functions are mapped on network applications. Such unauthorized activities are required to delete by deep packet inspection in application layer. The high level network equipment provides in-depth packet inspection through pattern matching in network detection system. Researchers have developed high performance parallel deep packet filters for reconfigurable devices. Although some reconfigurable systems can be generated automatically from pattern database, obtaining high performance result from each subsequent reconfiguration can be a time consuming process. By presenting a novel architecture for programmable centralized parallel pattern matching algorithm for efficient packet inspection with network processor and coprocessor in order to retrieve the pattern with less time. Produce a hybrid system that is able to update the rules immediate during the time the new filter is being compiled reduction of resource-intensive task and increasing bandwidth used snort rule. We mapped our centralized multi parallel pattern matching algorithm [CNMPPMA] for filter packet in parallel. The simulation result reveals that CNMPPMA significantly improves the matching performance. Also achieves the matching process with less cost.

Keywords

Intrusion Detection, Network Security, Pattern Matching, Packet Inspection.

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