Programmable Device Circuits and Systems

J. Ajayan ¹, S. Shriram ², D. Nirmal ³, K. Vivek ⁴

Affiliations
1 Electronics and Communication Engineering, Karunya University, IN
2 Electronics and Communication Engineering, MIT, Pondicherry, IN
3 Electronics and Communication Engineering Department, Karunya University, IN
4 Electronics and Communication Engineering, B. S. Abdur Rahman University, IN

Abstract

In this paper, a 128 bit high speed Manchester carry chain (MCC) adder is implemented using 22nm strained silicon technology with a supply voltage of 0.8V. The non-idealities such as variability and leakage current, may significantly degrade the performance of digital circuits as the technology approaches to nanometer regime. In this paper, the effect of temperature on the performance of the Manchester carry chain adder circuit is analyzed in detail and its performance is compared with the same circuit implemented using 90nm CMOS technology. The even and odd carries of the MCC adder are computed separately using two different carry chains. This will improves the operating speed of the adder. 8-Bit MCC adder modules are used for constructing 128 bit MCC adder.

Keywords

Carry Look-Ahead Adders, Domino Logic, High Performance, Leakage Currents, Manchester Carry Chain.

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J. Ajayan ¹, D. Jackuline Moni ²

Affiliations
1 Anna University, Tamilnadu, IN
2 Karunya University, Tamilnadu, IN

Abstract

In this paper, the performance of Symmetric Extended Source/Drain Schottky Tunneling Transistor (ESD-ST-SOIFET) with different gate structures are investigated through a TCAD modeling study and compared with the performances of STSFET and conventional CMOS devices. The Symmetric Extended Source/Drain Schottky Tunneling Transistor has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices.The aim is to improve the on current and reduce the leakage current of the low gate length devices. It is shown that, the doped extension regions adjacent to the source/drain schottky barrier improves the drive current by shrinking the schottky barrier and also the simulation results shows that the increasing doping levels at the source/drain(S/D) extensions increases the leakage current. The optimized device shows excellent short channel immunity, compared to conventional CMOS devices. Thus the optimal S/D design for high performance is more likely to be decided by practical considerations such as process integration. The analysis also shows that, the best characteristics of the proposed device can be obtained only if using proper silicides at the S/D regions. This paper presents the simulation study of ESD-ST-SOIFET. The silicide technology can be used for the fabrication of this device. This device is considered one of the most promising candidates for future nanotechnology world.

Keywords

Contact Resistance, High-K Gate Dielectrics, Nano Scale Devices, Semiconductor Device Modeling.

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