Programmable Device Circuits and Systems

N. Shylashree ¹, D. Venkata Narayana Reddy ², V. Sridhar ³

Affiliations
1 PESCE, Mandya, Karnataka, IN
2 RNSIT, Karnataka, IN
3 P.E.S College of Engineering, Mandya, Karnataka, IN

Abstract

RSA is one of the safest standard algorithms, based on public-key, for providing the security in communication and networks. One of the most time consuming processes in RSA algorithm for encryption/decryption is the modular exponentiation, i.e., Pemod n, where P is the text and (e,n) is the key. This paper examines how this computation could be speeded up by using Ancient Indian Vedic Mathematics when compared with the Booth algorithms. This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the sutras of Ancient Indian Vedic Mathematics and Booth multiplier. Compared to Booth multiplier, the Vedic multiplier occupies lesser area and achieves higher speed. Coding is done using Verilog-HDL and downloaded on targeted device as Virtex 5. Our proposed Vedic multiplier occupies lesser area and achieves higher speed than the previous work. Also, our proposed work is 3 times faster than the previous work when applied in RSA as is downloaded on targeted device Spartan 3.

Keywords

Booth Multiplier, Modular Multiplication, RSA Encryption/Decryption, Vedic Mathematics.

Full Text