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Chaudhari, Bharat S.
- A VHDL Implementation of Ternary Arithmetic and Logic Unit for Multi Valued Processor
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1 Pune Institute of Computer Technology, Pune, 411043, IN
2 Maharastra Institute of Technology, Pune, IN
3 Matoshri College of Engineering, Nasik, IN
1 Pune Institute of Computer Technology, Pune, 411043, IN
2 Maharastra Institute of Technology, Pune, IN
3 Matoshri College of Engineering, Nasik, IN