Programmable Device Circuits and Systems

Utsav H. Bhatt ¹, Ekata Mehul ¹, Anurag P. Lakhlani ¹, Amit  Kumar ¹

Affiliations
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN

Abstract

The paper present various possible jitter reduction technique while designing a Phase Locked Loop. Basic block which makes Phase Locked Loop are Phase detector, Loop Filter and Voltage Control Oscillator including suitable feedback. While reducing the jitter of PLL at the output, reduction in bandwidth of loop filter reducing the gain of phase detector, reducing the gain of the VCO, modifying basic building block and several other technique is proposed.

Keywords

Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).

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Brita K. Aslaliya ¹, Anurag P. Lakhlani ²

Affiliations
1 Department of Electronics and Communication, Marwadi Education Foundation’s Group of Institutions, Rajkot-360003 (Gujarat), IN
2 Marwadi Education Foundation’s Group of Institutions, Rajkot-360003 (Gujarat), IN

Abstract

In today's era a multiplier is a one of the key component of large number of systems such as micro-processors, digital signal processor, FIR (Finite Impulse Response) filters etc. Performance of multiplier of any system determined the performance of that system because the multiplier is generally slowest element and most area consuming. In this paper we compare three 8-bit multipliers such as Shift and Add multiplier, Booth multiplier and Vedic multiplier with the concentration on two key parameters Delay and Area. Different multipliers are synthesized and simulated on Xilinx 14.7 ISE Simulator and implemented on FPGA Spartan-6, xc6slx25t device. Shift and Add multiplier has a delay of 15.232 ns, Booth multiplier has a 20.643 ns and Vedic multiplier (Vertically and crosswise) has 12.651 ns of delay. Numbers of LUTs occupy by Shift and Add, Booth and Vedic multiplier are 88, 183 and 73 respectively. The result of this paper helps to choose a better multiplier from available options for fabricating different systems.

Keywords

Shift and Add Multiplier, Booth Multiplier Vedic Multipier-Urdhwa Tiryakbhyam Sutra.

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Utsav H. Bhatt ¹, Anurag P. Lakhlani ¹, Amit Kumar ¹

Affiliations
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, IN

Abstract

The paper presents a designing a low jitter Phase Locked Loop (PLL). To reduce the jitter design is modified such that it gives minimal phase variation at the output of voltage controlled oscillator. The design uses phase frequency detector with charge pump configuration. The current source output of charge pump given to the current starved voltage controlled oscillator. The VCO is design of 100 Mhz with 50 nm technology BSIM4 model used for simulation in LTSpice. The design has advantage in lower area as well as faster acquisition time of PLL.

Keywords

Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).

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