Programmable Device Circuits and Systems

Abstract

The paper presented here exhibits a modern ADC (analog-to-digital converter) BIST (built-in self test) scheme using code-width with sample difference testing technique. The BIST scheme proposed here is employed on 8-bit sigma-delta ADC which is implemented by using first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter. The proposed BIST scheme is certified by simulation of the 8 bit sigma-delta ADC with arbitrary faults. The measurements of Differential Non Linearity (DNL), monotonicity fault and missing code fault have been detected. Power consumed in the proposed BIST circuit is 18mW for the given power supply of 1V. The output is shown at the output of OR gate denoted as 'F'.  In order to implement the BIST scheme considered in this paper, an 8 sigma-delta ADC and also the other components were designed in Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology.

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