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A Low Power Threshold Inverter Quantizer Comparator Using Diode Free Adiabatic Logic for 1.2 V, 3-Bit Flash Analog to Digital Converter


Affiliations
1 Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Shri Shankaracharya Institute of Tech. & Mgmt. Bhilai, India
2 Shri Shankaracharya Technical Campus, Shri Shankaracharya Engineering College, Bhilai, India
     

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Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is recommended in this paper for implementation of a 3-bit Flash type Analog to Digital Converter. The advised work is simulated with TSMC-65nm Technology on Cadence tool. For appropriate implement of DFAL-TIQ, it is requisite to have a suitable reference voltage for each of the comparator and it is done by accurately sizing the transistors of the comparators. The average power consumed by the advised Flash type ADC when simulated at 100 Hz, 1.2Vpp and for 1fF capacitive load is 5.53 µW, which is 66.03 % lesser than that of the power consumed by Flash ADC containing conventional CMOS-TIQ comparator, and the static parameters observed as: DNL = + 0.56 LSB /-0.61 LSB and INL = +0.40 LSB /-0.43 LSB, respectively.


Keywords

Diode Free Adiabatic Logic-DFAL, Analog to Digital Converter-ADC, Threshold Inverter Quantizer-TIQ, Least Significant Bit-LSB, Most Significant Bit-MSB, Electrocardiogram-ECG, Differential Non Linearity-DNL, Integral Non Linearity-INL.
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  • A Low Power Threshold Inverter Quantizer Comparator Using Diode Free Adiabatic Logic for 1.2 V, 3-Bit Flash Analog to Digital Converter

Abstract Views: 179  |  PDF Views: 3

Authors

Vishal Moyal
Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Shri Shankaracharya Institute of Tech. & Mgmt. Bhilai, India
Neeta Tripathi
Shri Shankaracharya Technical Campus, Shri Shankaracharya Engineering College, Bhilai, India

Abstract


Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is recommended in this paper for implementation of a 3-bit Flash type Analog to Digital Converter. The advised work is simulated with TSMC-65nm Technology on Cadence tool. For appropriate implement of DFAL-TIQ, it is requisite to have a suitable reference voltage for each of the comparator and it is done by accurately sizing the transistors of the comparators. The average power consumed by the advised Flash type ADC when simulated at 100 Hz, 1.2Vpp and for 1fF capacitive load is 5.53 µW, which is 66.03 % lesser than that of the power consumed by Flash ADC containing conventional CMOS-TIQ comparator, and the static parameters observed as: DNL = + 0.56 LSB /-0.61 LSB and INL = +0.40 LSB /-0.43 LSB, respectively.


Keywords


Diode Free Adiabatic Logic-DFAL, Analog to Digital Converter-ADC, Threshold Inverter Quantizer-TIQ, Least Significant Bit-LSB, Most Significant Bit-MSB, Electrocardiogram-ECG, Differential Non Linearity-DNL, Integral Non Linearity-INL.