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Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem


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1 Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
     

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The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam theorem. The design of the aforementioned multiplier has been carried out using Modified-Gate-Diffusion-Input cells, which facilitate the reduction of the transistor count while maintaining a full voltage-swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier.

Keywords

Area-Efficient, CMOS, Gate Diffusion Input, Low-Power, Multiplier, Urdhva-Tiryagbhyam Theorem.
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  • Somani, A., Jain, D., Jaiswal, S., Verma, K. and Kasht, S., “Compare Vedic Multipliers with Conventional Hierarchical array of array multiplier”, International Journal of Computer Technology and Electronics Engineering, Vol. 2, No. 6, pp. 52-55, 2012.

  • Morgenshtein, A., Fish, A. and Wagner, I., “Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 5, pp. 566-581, 2002.

  • Kumari, R. and Mehra, R., “Power and Delay Analysis of CMOS Multipliers using Vedic Algorithm”, International Conference on Power Electronics, Intelligent Control and Energy Systems, Vol. 1, pp. 1-6, 2016.

  • Gadakh, S.N. and Khade, S., “Design and Optimization of 16x16 Bit Multiplier using Vedic Mathematics”, International Conference on Automatic Control and Dynamic Optimization Techniques, pp. 184-187, 2016.

  • Narendra, K. and Pandu, S., “Low Power Area-Efficient Adiabatic Vedic Multiplier”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 03, No. 08, pp. 11027-11032, 2014.

  • G. Deshpande, N. and Mahajan, R., “Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors”, International Journal of Computer Applications, Vol. 95, No. 24, pp. 19-22, 2014.

  • Latha, B. and Rao, B., “Design and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 03 No. 08, pp. 11601-11609, 2014.

  • Kareem, A., M., V. and Kumar, P., “VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques”, Recent Patents on Computer Science, Vol. 9, No. 3, pp. 216-221, 2017.

  • Manikrao, K. and Shrikant, M., “Analysis of Array Multiplier and Vedic Multiplier using Xilinx”, Communications on Applied Electronics, Vol. 5, No. 1, pp. 13-16, 2016.

  • Kaur, S., Singh, B. and D.K, J., “Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique”, International Journal of VLSI Design & Communication Systems, Vol. 6, No. 5, pp. 45-56, 2015.

  • Rashmi, D.S., Rukhsar, R.S., Shilpa, H.R., Vidyashree, C.R., Kunjan, D.S. and Nithin. H.V., “Modelling of Adders using CMOS and GDI Logic for multiplier applications: A VLSI based approach”, International Conference on Circuit, Power and Computing Technologies, pp. 1-6, 2016.

  • Mohan, S. and Rangaswamy N., “GDI based full adders for energy efficient arithmetic applications”, Engineering Science and Technology, an International Journal, Vol. 19, pp. 485-496, 2016.

  • Sadeghi, H., Jirandeh, H.M. and Zakeri, A., “Improvement in Sub-circuit of Full Adder Cell (XOR and XNOR) by GDI and FinFET Structure”, International Journal of Scientific & Engineering Research, Vol. 05 No. 05, pp. 162-165, 2014.

  • Nicholas, A., Williams, K. and Pickles, J., Vertically and Crosswise. Castle Douglas, Scotland UK: Inspiration Books, 2010.

  • Williams, K. and Gaskell, M., The Cosmic Computer. Skelmersdale: Inspiration Books, 1997.

  • Weste, N. and Harris, D., Principles of CMOS VLSI Design. Pearson Education India, 2011.


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  • Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem

Abstract Views: 179  |  PDF Views: 2

Authors

Bobby Nelson
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
Ravi Tiwari
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India

Abstract


The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam theorem. The design of the aforementioned multiplier has been carried out using Modified-Gate-Diffusion-Input cells, which facilitate the reduction of the transistor count while maintaining a full voltage-swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier.

Keywords


Area-Efficient, CMOS, Gate Diffusion Input, Low-Power, Multiplier, Urdhva-Tiryagbhyam Theorem.

References