Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Static and Dynamic Parameter Estimation of Stacked CMOS Inverter based TIQ for Flash ADC


     

   Subscribe/Renew Journal


This paper aims to estimate parameters of a 3-bit Flash Analog to Digital Converter (ADC) using Threshold Inverter Quantizer (TIQ) technique implemented with stacked CMOS Inverter. The stacked TIQ based flash ADC requires 2n-1 comparators like conventional ADCs. Though, each comparator in the TIQ flash ADC has different sizes to cater internal reference voltages, which is achieved by systematically varying widths of PMOS and NMOS transistors of TIQ inverter, as a result 70% reduction of power consumption is achieved. The static and dynamic parameter are evaluated for the implemented design and obtained result as follows DNL = ± 0.23 LSB, INL = ± 0.15 LSB, SNR= 17.38 dB, SFDR = 21.98 dB and ENOB = 2.5 bits. The design consumes 5.98 µW power when simulated at 1 KHz, 1.2Vpp input signal at Vdd = 1.2V dc with load capacitance of 1fF.  


Keywords

ADC, TIQ, CMOS, PMOS, NMOS, VTC, MUX, LSB, DNL, INL, SNR, SFDR, ENOB.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 164

PDF Views: 2




  • Static and Dynamic Parameter Estimation of Stacked CMOS Inverter based TIQ for Flash ADC

Abstract Views: 164  |  PDF Views: 2

Authors

Abstract


This paper aims to estimate parameters of a 3-bit Flash Analog to Digital Converter (ADC) using Threshold Inverter Quantizer (TIQ) technique implemented with stacked CMOS Inverter. The stacked TIQ based flash ADC requires 2n-1 comparators like conventional ADCs. Though, each comparator in the TIQ flash ADC has different sizes to cater internal reference voltages, which is achieved by systematically varying widths of PMOS and NMOS transistors of TIQ inverter, as a result 70% reduction of power consumption is achieved. The static and dynamic parameter are evaluated for the implemented design and obtained result as follows DNL = ± 0.23 LSB, INL = ± 0.15 LSB, SNR= 17.38 dB, SFDR = 21.98 dB and ENOB = 2.5 bits. The design consumes 5.98 µW power when simulated at 1 KHz, 1.2Vpp input signal at Vdd = 1.2V dc with load capacitance of 1fF.  


Keywords


ADC, TIQ, CMOS, PMOS, NMOS, VTC, MUX, LSB, DNL, INL, SNR, SFDR, ENOB.